677 lines
17 KiB
C
677 lines
17 KiB
C
/* linux/drivers/mmc/host/sdhci-s3c.c
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*
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* Copyright 2008 Openmoko Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* SDHCI (HSMMC) support for Samsung SoC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/mmc/host.h>
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#include <plat/sdhci.h>
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#include <plat/regs-sdhci.h>
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#include "sdhci.h"
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#define MAX_BUS_CLK (4)
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/**
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* struct sdhci_s3c - S3C SDHCI instance
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* @host: The SDHCI host created
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* @pdev: The platform device we where created from.
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* @ioarea: The resource created when we claimed the IO area.
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* @pdata: The platform data for this controller.
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* @cur_clk: The index of the current bus clock.
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* @clk_io: The clock for the internal bus interface.
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* @clk_bus: The clocks that are available for the SD/MMC bus clock.
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*/
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struct sdhci_s3c {
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struct sdhci_host *host;
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struct platform_device *pdev;
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struct resource *ioarea;
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struct s3c_sdhci_platdata *pdata;
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unsigned int cur_clk;
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int ext_cd_irq;
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int ext_cd_gpio;
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struct clk *clk_io;
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struct clk *clk_bus[MAX_BUS_CLK];
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};
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static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
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{
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return sdhci_priv(host);
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}
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/**
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* get_curclk - convert ctrl2 register to clock source number
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* @ctrl2: Control2 register value.
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*/
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static u32 get_curclk(u32 ctrl2)
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{
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ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
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ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
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return ctrl2;
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}
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static void sdhci_s3c_check_sclk(struct sdhci_host *host)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
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if (get_curclk(tmp) != ourhost->cur_clk) {
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dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
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tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
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tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
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writel(tmp, host->ioaddr + 0x80);
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}
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}
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/**
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* sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
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* @host: The SDHCI host instance.
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*
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* Callback to return the maximum clock rate acheivable by the controller.
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*/
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static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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struct clk *busclk;
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unsigned int rate, max;
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int clk;
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/* note, a reset will reset the clock source */
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sdhci_s3c_check_sclk(host);
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for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
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busclk = ourhost->clk_bus[clk];
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if (!busclk)
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continue;
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rate = clk_get_rate(busclk);
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if (rate > max)
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max = rate;
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}
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return max;
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}
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/**
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* sdhci_s3c_consider_clock - consider one the bus clocks for current setting
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* @ourhost: Our SDHCI instance.
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* @src: The source clock index.
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* @wanted: The clock frequency wanted.
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*/
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static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
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unsigned int src,
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unsigned int wanted)
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{
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unsigned long rate;
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struct clk *clksrc = ourhost->clk_bus[src];
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int div;
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if (!clksrc)
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return UINT_MAX;
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/*
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* Clock divider's step is different as 1 from that of host controller
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* when 'clk_type' is S3C_SDHCI_CLK_DIV_EXTERNAL.
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*/
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if (ourhost->pdata->clk_type) {
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rate = clk_round_rate(clksrc, wanted);
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return wanted - rate;
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}
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rate = clk_get_rate(clksrc);
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for (div = 1; div < 256; div *= 2) {
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if ((rate / div) <= wanted)
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break;
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}
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dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
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src, rate, wanted, rate / div);
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return (wanted - (rate / div));
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}
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/**
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* sdhci_s3c_set_clock - callback on clock change
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* @host: The SDHCI host being changed
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* @clock: The clock rate being requested.
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*
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* When the card's clock is going to be changed, look at the new frequency
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* and find the best clock source to go with it.
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*/
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static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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unsigned int best = UINT_MAX;
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unsigned int delta;
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int best_src = 0;
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int src;
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u32 ctrl;
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/* don't bother if the clock is going off. */
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if (clock == 0)
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return;
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for (src = 0; src < MAX_BUS_CLK; src++) {
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delta = sdhci_s3c_consider_clock(ourhost, src, clock);
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if (delta < best) {
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best = delta;
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best_src = src;
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}
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}
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dev_dbg(&ourhost->pdev->dev,
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"selected source %d, clock %d, delta %d\n",
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best_src, clock, best);
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/* select the new clock source */
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if (ourhost->cur_clk != best_src) {
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struct clk *clk = ourhost->clk_bus[best_src];
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/* turn clock off to card before changing clock source */
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writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
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ourhost->cur_clk = best_src;
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host->max_clk = clk_get_rate(clk);
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ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
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ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
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ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
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writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
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}
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/* reprogram default hardware configuration */
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writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
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host->ioaddr + S3C64XX_SDHCI_CONTROL4);
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ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
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ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
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S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
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S3C_SDHCI_CTRL2_ENFBCLKRX |
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S3C_SDHCI_CTRL2_DFCNT_NONE |
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S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
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writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
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/* reconfigure the controller for new clock rate */
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ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
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if (clock < 25 * 1000000)
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ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
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writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
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}
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/**
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* sdhci_s3c_get_min_clock - callback to get minimal supported clock value
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* @host: The SDHCI host being queried
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*
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* To init mmc host properly a minimal clock value is needed. For high system
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* bus clock's values the standard formula gives values out of allowed range.
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* The clock still can be set to lower values, if clock source other then
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* system bus is selected.
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*/
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static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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unsigned int delta, min = UINT_MAX;
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int src;
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for (src = 0; src < MAX_BUS_CLK; src++) {
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delta = sdhci_s3c_consider_clock(ourhost, src, 0);
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if (delta == UINT_MAX)
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continue;
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/* delta is a negative value in this case */
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if (-delta < min)
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min = -delta;
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}
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return min;
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}
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/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
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static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX);
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}
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/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
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static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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/*
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* initial clock can be in the frequency range of
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* 100KHz-400KHz, so we set it as max value.
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*/
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return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000);
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}
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/* sdhci_cmu_set_clock - callback on clock change.*/
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static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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/* don't bother if the clock is going off */
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if (clock == 0)
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return;
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sdhci_s3c_set_clock(host, clock);
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clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
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host->clock = clock;
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}
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/**
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* sdhci_s3c_platform_8bit_width - support 8bit buswidth
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* @host: The SDHCI host being queried
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* @width: MMC_BUS_WIDTH_ macro for the bus width being requested
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*
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* We have 8-bit width support but is not a v3 controller.
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* So we add platform_8bit_width() and support 8bit width.
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*/
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static int sdhci_s3c_platform_8bit_width(struct sdhci_host *host, int width)
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{
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u8 ctrl;
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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switch (width) {
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case MMC_BUS_WIDTH_8:
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ctrl |= SDHCI_CTRL_8BITBUS;
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ctrl &= ~SDHCI_CTRL_4BITBUS;
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break;
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case MMC_BUS_WIDTH_4:
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ctrl |= SDHCI_CTRL_4BITBUS;
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ctrl &= ~SDHCI_CTRL_8BITBUS;
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break;
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default:
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ctrl &= ~SDHCI_CTRL_4BITBUS;
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ctrl &= ~SDHCI_CTRL_8BITBUS;
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break;
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}
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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return 0;
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}
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static struct sdhci_ops sdhci_s3c_ops = {
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.get_max_clock = sdhci_s3c_get_max_clk,
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.set_clock = sdhci_s3c_set_clock,
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.get_min_clock = sdhci_s3c_get_min_clock,
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.platform_8bit_width = sdhci_s3c_platform_8bit_width,
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};
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static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
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{
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struct sdhci_host *host = platform_get_drvdata(dev);
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unsigned long flags;
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if (host) {
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spin_lock_irqsave(&host->lock, flags);
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if (state) {
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dev_dbg(&dev->dev, "card inserted.\n");
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host->flags &= ~SDHCI_DEVICE_DEAD;
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host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
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} else {
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dev_dbg(&dev->dev, "card removed.\n");
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host->flags |= SDHCI_DEVICE_DEAD;
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host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
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}
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tasklet_schedule(&host->card_tasklet);
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spin_unlock_irqrestore(&host->lock, flags);
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}
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}
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static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id)
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{
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struct sdhci_s3c *sc = dev_id;
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int status = gpio_get_value(sc->ext_cd_gpio);
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if (sc->pdata->ext_cd_gpio_invert)
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status = !status;
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sdhci_s3c_notify_change(sc->pdev, status);
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return IRQ_HANDLED;
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}
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static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
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{
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struct s3c_sdhci_platdata *pdata = sc->pdata;
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struct device *dev = &sc->pdev->dev;
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if (gpio_request(pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) {
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sc->ext_cd_gpio = pdata->ext_cd_gpio;
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sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio);
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if (sc->ext_cd_irq &&
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request_threaded_irq(sc->ext_cd_irq, NULL,
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sdhci_s3c_gpio_card_detect_thread,
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IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
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dev_name(dev), sc) == 0) {
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int status = gpio_get_value(sc->ext_cd_gpio);
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if (pdata->ext_cd_gpio_invert)
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status = !status;
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sdhci_s3c_notify_change(sc->pdev, status);
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} else {
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dev_warn(dev, "cannot request irq for card detect\n");
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sc->ext_cd_irq = 0;
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}
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} else {
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dev_err(dev, "cannot request gpio for card detect\n");
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}
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}
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static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
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{
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struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
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struct device *dev = &pdev->dev;
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struct sdhci_host *host;
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struct sdhci_s3c *sc;
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struct resource *res;
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int ret, irq, ptr, clks;
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if (!pdata) {
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dev_err(dev, "no device data specified\n");
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return -ENOENT;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(dev, "no irq specified\n");
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return irq;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(dev, "no memory specified\n");
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return -ENOENT;
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}
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host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
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if (IS_ERR(host)) {
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dev_err(dev, "sdhci_alloc_host() failed\n");
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return PTR_ERR(host);
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}
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sc = sdhci_priv(host);
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sc->host = host;
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sc->pdev = pdev;
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sc->pdata = pdata;
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sc->ext_cd_gpio = -1; /* invalid gpio number */
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platform_set_drvdata(pdev, host);
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sc->clk_io = clk_get(dev, "hsmmc");
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if (IS_ERR(sc->clk_io)) {
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dev_err(dev, "failed to get io clock\n");
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ret = PTR_ERR(sc->clk_io);
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goto err_io_clk;
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}
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/* enable the local io clock and keep it running for the moment. */
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clk_enable(sc->clk_io);
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for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
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struct clk *clk;
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char *name = pdata->clocks[ptr];
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if (name == NULL)
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continue;
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clk = clk_get(dev, name);
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to get clock %s\n", name);
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continue;
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}
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clks++;
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sc->clk_bus[ptr] = clk;
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/*
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* save current clock index to know which clock bus
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* is used later in overriding functions.
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*/
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sc->cur_clk = ptr;
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clk_enable(clk);
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dev_info(dev, "clock source %d: %s (%ld Hz)\n",
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ptr, name, clk_get_rate(clk));
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}
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if (clks == 0) {
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dev_err(dev, "failed to find any bus clocks\n");
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ret = -ENOENT;
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goto err_no_busclks;
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}
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sc->ioarea = request_mem_region(res->start, resource_size(res),
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mmc_hostname(host->mmc));
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if (!sc->ioarea) {
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dev_err(dev, "failed to reserve register area\n");
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ret = -ENXIO;
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goto err_req_regs;
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}
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host->ioaddr = ioremap_nocache(res->start, resource_size(res));
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if (!host->ioaddr) {
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dev_err(dev, "failed to map registers\n");
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ret = -ENXIO;
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goto err_req_regs;
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}
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/* Ensure we have minimal gpio selected CMD/CLK/Detect */
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if (pdata->cfg_gpio)
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pdata->cfg_gpio(pdev, pdata->max_width);
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host->hw_name = "samsung-hsmmc";
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host->ops = &sdhci_s3c_ops;
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host->quirks = 0;
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host->irq = irq;
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/* Setup quirks for the controller */
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host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
|
|
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
|
|
|
|
#ifndef CONFIG_MMC_SDHCI_S3C_DMA
|
|
|
|
/* we currently see overruns on errors, so disable the SDMA
|
|
* support as well. */
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
|
|
|
|
#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
|
|
|
|
/* It seems we do not get an DATA transfer complete on non-busy
|
|
* transfers, not sure if this is a problem with this specific
|
|
* SDHCI block, or a missing configuration that needs to be set. */
|
|
host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
|
|
|
|
/* This host supports the Auto CMD12 */
|
|
host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
|
|
|
|
/* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
|
|
|
|
if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
|
|
pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
|
|
|
|
if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
|
|
host->mmc->caps = MMC_CAP_NONREMOVABLE;
|
|
|
|
if (pdata->host_caps)
|
|
host->mmc->caps |= pdata->host_caps;
|
|
|
|
host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
|
|
SDHCI_QUIRK_32BIT_DMA_SIZE);
|
|
|
|
/* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
|
|
host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
|
|
|
|
/*
|
|
* If controller does not have internal clock divider,
|
|
* we can use overriding functions instead of default.
|
|
*/
|
|
if (pdata->clk_type) {
|
|
sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
|
|
sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
|
|
sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
|
|
}
|
|
|
|
/* It supports additional host capabilities if needed */
|
|
if (pdata->host_caps)
|
|
host->mmc->caps |= pdata->host_caps;
|
|
|
|
ret = sdhci_add_host(host);
|
|
if (ret) {
|
|
dev_err(dev, "sdhci_add_host() failed\n");
|
|
goto err_add_host;
|
|
}
|
|
|
|
/* The following two methods of card detection might call
|
|
sdhci_s3c_notify_change() immediately, so they can be called
|
|
only after sdhci_add_host(). Setup errors are ignored. */
|
|
if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
|
|
pdata->ext_cd_init(&sdhci_s3c_notify_change);
|
|
if (pdata->cd_type == S3C_SDHCI_CD_GPIO &&
|
|
gpio_is_valid(pdata->ext_cd_gpio))
|
|
sdhci_s3c_setup_card_detect_gpio(sc);
|
|
|
|
return 0;
|
|
|
|
err_add_host:
|
|
release_resource(sc->ioarea);
|
|
kfree(sc->ioarea);
|
|
|
|
err_req_regs:
|
|
for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
|
|
if (sc->clk_bus[ptr]) {
|
|
clk_disable(sc->clk_bus[ptr]);
|
|
clk_put(sc->clk_bus[ptr]);
|
|
}
|
|
}
|
|
|
|
err_no_busclks:
|
|
clk_disable(sc->clk_io);
|
|
clk_put(sc->clk_io);
|
|
|
|
err_io_clk:
|
|
sdhci_free_host(host);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
|
|
{
|
|
struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_s3c *sc = sdhci_priv(host);
|
|
int ptr;
|
|
|
|
if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
|
|
pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
|
|
|
|
if (sc->ext_cd_irq)
|
|
free_irq(sc->ext_cd_irq, sc);
|
|
|
|
if (gpio_is_valid(sc->ext_cd_gpio))
|
|
gpio_free(sc->ext_cd_gpio);
|
|
|
|
sdhci_remove_host(host, 1);
|
|
|
|
for (ptr = 0; ptr < 3; ptr++) {
|
|
if (sc->clk_bus[ptr]) {
|
|
clk_disable(sc->clk_bus[ptr]);
|
|
clk_put(sc->clk_bus[ptr]);
|
|
}
|
|
}
|
|
clk_disable(sc->clk_io);
|
|
clk_put(sc->clk_io);
|
|
|
|
iounmap(host->ioaddr);
|
|
release_resource(sc->ioarea);
|
|
kfree(sc->ioarea);
|
|
|
|
sdhci_free_host(host);
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int sdhci_s3c_suspend(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
|
|
return sdhci_suspend_host(host);
|
|
}
|
|
|
|
static int sdhci_s3c_resume(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
|
|
return sdhci_resume_host(host);
|
|
}
|
|
|
|
static const struct dev_pm_ops sdhci_s3c_pmops = {
|
|
.suspend = sdhci_s3c_suspend,
|
|
.resume = sdhci_s3c_resume,
|
|
};
|
|
|
|
#define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
|
|
|
|
#else
|
|
#define SDHCI_S3C_PMOPS NULL
|
|
#endif
|
|
|
|
static struct platform_driver sdhci_s3c_driver = {
|
|
.probe = sdhci_s3c_probe,
|
|
.remove = __devexit_p(sdhci_s3c_remove),
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "s3c-sdhci",
|
|
.pm = SDHCI_S3C_PMOPS,
|
|
},
|
|
};
|
|
|
|
static int __init sdhci_s3c_init(void)
|
|
{
|
|
return platform_driver_register(&sdhci_s3c_driver);
|
|
}
|
|
|
|
static void __exit sdhci_s3c_exit(void)
|
|
{
|
|
platform_driver_unregister(&sdhci_s3c_driver);
|
|
}
|
|
|
|
module_init(sdhci_s3c_init);
|
|
module_exit(sdhci_s3c_exit);
|
|
|
|
MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
|
|
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:s3c-sdhci");
|