ce3a161e69
Most of these guys are simply not needed (pulled by other stuff via asm-i386/hardirq.h). One that is not entirely useless is hilarious - arch/i386/oprofile/nmi_timer_int.c includes linux/irq.h... as a way to get linux/errno.h Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
/*
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* Unmaintained SGI Visual Workstation support.
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* Split out from setup.c by davej@suse.de
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*/
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#include <linux/smp.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/fixmap.h>
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#include <asm/arch_hooks.h>
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#include <asm/io.h>
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#include "cobalt.h"
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#include "piix4.h"
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int no_broadcast;
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char visws_board_type = -1;
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char visws_board_rev = -1;
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void __init visws_get_board_type_and_rev(void)
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{
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int raw;
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visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
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>> PIIX_GPI_BD_SHIFT;
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/*
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* Get Board rev.
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* First, we have to initialize the 307 part to allow us access
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* to the GPIO registers. Let's map them at 0x0fc0 which is right
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* after the PIIX4 PM section.
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*/
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outb_p(SIO_DEV_SEL, SIO_INDEX);
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outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
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outb_p(SIO_DEV_MSB, SIO_INDEX);
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outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
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outb_p(SIO_DEV_LSB, SIO_INDEX);
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outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
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outb_p(SIO_DEV_ENB, SIO_INDEX);
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outb_p(1, SIO_DATA); /* Enable GPIO registers. */
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/*
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* Now, we have to map the power management section to write
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* a bit which enables access to the GPIO registers.
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* What lunatic came up with this shit?
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*/
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outb_p(SIO_DEV_SEL, SIO_INDEX);
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outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
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outb_p(SIO_DEV_MSB, SIO_INDEX);
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outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
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outb_p(SIO_DEV_LSB, SIO_INDEX);
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outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
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outb_p(SIO_DEV_ENB, SIO_INDEX);
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outb_p(1, SIO_DATA); /* Enable PM registers. */
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/*
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* Now, write the PM register which enables the GPIO registers.
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*/
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outb_p(SIO_PM_FER2, SIO_PM_INDEX);
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outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
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/*
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* Now, initialize the GPIO registers.
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* We want them all to be inputs which is the
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* power on default, so let's leave them alone.
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* So, let's just read the board rev!
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*/
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raw = inb_p(SIO_GP_DATA1);
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raw &= 0x7f; /* 7 bits of valid board revision ID. */
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if (visws_board_type == VISWS_320) {
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if (raw < 0x6) {
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visws_board_rev = 4;
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} else if (raw < 0xc) {
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visws_board_rev = 5;
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} else {
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visws_board_rev = 6;
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}
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} else if (visws_board_type == VISWS_540) {
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visws_board_rev = 2;
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} else {
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visws_board_rev = raw;
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}
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printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
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(visws_board_type == VISWS_320 ? "320" :
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(visws_board_type == VISWS_540 ? "540" :
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"unknown")), visws_board_rev);
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}
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void __init pre_intr_init_hook(void)
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{
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init_VISWS_APIC_irqs();
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}
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void __init intr_init_hook(void)
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{
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#ifdef CONFIG_X86_LOCAL_APIC
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apic_intr_init();
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#endif
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}
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void __init pre_setup_arch_hook()
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{
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visws_get_board_type_and_rev();
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}
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static struct irqaction irq0 = {
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.handler = timer_interrupt,
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.flags = SA_INTERRUPT,
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.name = "timer",
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};
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void __init time_init_hook(void)
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{
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printk(KERN_INFO "Starting Cobalt Timer system clock\n");
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/* Set the countdown value */
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co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
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/* Start the timer */
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co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
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/* Enable (unmask) the timer interrupt */
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co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
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/* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */
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setup_irq(0, &irq0);
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}
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