d882b17251
Put s390's syscall tables into .rodata section and write protect this section to prevent misuse of it. Suggested by Arjan van de Ven <arjan@infradead.org>. Cc: Arjan van de Ven <arjan@infradead.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
1006 lines
31 KiB
ArmAsm
1006 lines
31 KiB
ArmAsm
/*
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* arch/s390/kernel/entry64.S
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* S390 low-level entry points.
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*
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* Copyright (C) IBM Corp. 1999,2006
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
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* Hartmut Penner (hp@de.ibm.com),
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* Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
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* Heiko Carstens <heiko.carstens@de.ibm.com>
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/cache.h>
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#include <asm/lowcore.h>
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#include <asm/errno.h>
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/unistd.h>
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#include <asm/page.h>
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/*
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* Stack layout for the system_call stack entry.
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* The first few entries are identical to the user_regs_struct.
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*/
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SP_PTREGS = STACK_FRAME_OVERHEAD
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SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
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SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
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SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
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SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
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SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
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SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
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SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
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SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
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SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
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SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
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SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
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SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
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SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
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SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
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SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
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SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
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SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
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SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
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SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
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SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
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SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP
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SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
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STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
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STACK_SIZE = 1 << STACK_SHIFT
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_TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \
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_TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
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_TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \
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_TIF_MCCK_PENDING)
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#define BASED(name) name-system_call(%r13)
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.macro STORE_TIMER lc_offset
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#ifdef CONFIG_VIRT_CPU_ACCOUNTING
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stpt \lc_offset
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#endif
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.endm
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#ifdef CONFIG_VIRT_CPU_ACCOUNTING
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.macro UPDATE_VTIME lc_from,lc_to,lc_sum
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lg %r10,\lc_from
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slg %r10,\lc_to
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alg %r10,\lc_sum
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stg %r10,\lc_sum
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.endm
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#endif
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/*
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* Register usage in interrupt handlers:
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* R9 - pointer to current task structure
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* R13 - pointer to literal pool
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* R14 - return register for function calls
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* R15 - kernel stack pointer
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*/
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.macro SAVE_ALL_BASE savearea
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stmg %r12,%r15,\savearea
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larl %r13,system_call
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.endm
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.macro SAVE_ALL_SYNC psworg,savearea
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la %r12,\psworg
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tm \psworg+1,0x01 # test problem state bit
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jz 2f # skip stack setup save
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lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
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#ifdef CONFIG_CHECK_STACK
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j 3f
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2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
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jz stack_overflow
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3:
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#endif
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2:
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.endm
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.macro SAVE_ALL_ASYNC psworg,savearea
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la %r12,\psworg
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tm \psworg+1,0x01 # test problem state bit
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jnz 1f # from user -> load kernel stack
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clc \psworg+8(8),BASED(.Lcritical_end)
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jhe 0f
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clc \psworg+8(8),BASED(.Lcritical_start)
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jl 0f
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brasl %r14,cleanup_critical
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tm 1(%r12),0x01 # retest problem state after cleanup
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jnz 1f
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0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
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slgr %r14,%r15
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srag %r14,%r14,STACK_SHIFT
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jz 2f
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1: lg %r15,__LC_ASYNC_STACK # load async stack
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#ifdef CONFIG_CHECK_STACK
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j 3f
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2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
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jz stack_overflow
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3:
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#endif
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2:
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.endm
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.macro CREATE_STACK_FRAME psworg,savearea
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aghi %r15,-SP_SIZE # make room for registers & psw
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mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
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la %r12,\psworg
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stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
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icm %r12,12,__LC_SVC_ILC
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stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
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st %r12,SP_ILC(%r15)
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mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack
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la %r12,0
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stg %r12,__SF_BACKCHAIN(%r15)
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.endm
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.macro RESTORE_ALL psworg,sync
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mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
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.if !\sync
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ni \psworg+1,0xfd # clear wait state bit
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.endif
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lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user
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STORE_TIMER __LC_EXIT_TIMER
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lpswe \psworg # back to caller
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.endm
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/*
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* Scheduler resume function, called by switch_to
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* gpr2 = (task_struct *) prev
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* gpr3 = (task_struct *) next
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* Returns:
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* gpr2 = prev
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*/
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.globl __switch_to
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__switch_to:
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tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
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jz __switch_to_noper # if not we're fine
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stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
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clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
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je __switch_to_noper # we got away without bashing TLB's
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lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
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__switch_to_noper:
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lg %r4,__THREAD_info(%r2) # get thread_info of prev
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tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
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jz __switch_to_no_mcck
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ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
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lg %r4,__THREAD_info(%r3) # get thread_info of next
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oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
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__switch_to_no_mcck:
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stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
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stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
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lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
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lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
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stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
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lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
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lg %r3,__THREAD_info(%r3) # load thread_info from task struct
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stg %r3,__LC_THREAD_INFO
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aghi %r3,STACK_SIZE
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stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
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br %r14
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__critical_start:
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/*
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* SVC interrupt handler routine. System calls are synchronous events and
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* are executed with interrupts enabled.
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*/
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.globl system_call
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system_call:
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STORE_TIMER __LC_SYNC_ENTER_TIMER
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sysc_saveall:
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SAVE_ALL_BASE __LC_SAVE_AREA
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SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
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CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
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llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
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#ifdef CONFIG_VIRT_CPU_ACCOUNTING
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sysc_vtime:
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tm SP_PSW+1(%r15),0x01 # interrupting from user ?
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jz sysc_do_svc
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UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
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sysc_stime:
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UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
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sysc_update:
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mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
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#endif
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sysc_do_svc:
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lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
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slag %r7,%r7,2 # *4 and test for svc 0
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jnz sysc_nr_ok
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# svc 0: system call number in %r1
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cl %r1,BASED(.Lnr_syscalls)
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jnl sysc_nr_ok
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lgfr %r7,%r1 # clear high word in r1
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slag %r7,%r7,2 # svc 0: system call number in %r1
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sysc_nr_ok:
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mvc SP_ARGS(8,%r15),SP_R7(%r15)
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sysc_do_restart:
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larl %r10,sys_call_table
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#ifdef CONFIG_COMPAT
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tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ?
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jno sysc_noemu
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larl %r10,sys_call_table_emu # use 31 bit emulation system calls
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sysc_noemu:
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#endif
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tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
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lgf %r8,0(%r7,%r10) # load address of system call routine
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jnz sysc_tracesys
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basr %r14,%r8 # call sys_xxxx
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stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
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# ATTENTION: check sys_execve_glue before
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# changing anything here !!
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sysc_return:
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tm SP_PSW+1(%r15),0x01 # returning to user ?
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jno sysc_leave
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tm __TI_flags+7(%r9),_TIF_WORK_SVC
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jnz sysc_work # there is work to do (signals etc.)
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sysc_leave:
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RESTORE_ALL __LC_RETURN_PSW,1
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#
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# recheck if there is more work to do
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#
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sysc_work_loop:
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tm __TI_flags+7(%r9),_TIF_WORK_SVC
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jz sysc_leave # there is no work to do
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#
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# One of the work bits is on. Find out which one.
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#
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sysc_work:
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tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
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jo sysc_mcck_pending
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tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
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jo sysc_reschedule
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tm __TI_flags+7(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK)
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jnz sysc_sigpending
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tm __TI_flags+7(%r9),_TIF_RESTART_SVC
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jo sysc_restart
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tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
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jo sysc_singlestep
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j sysc_leave
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#
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# _TIF_NEED_RESCHED is set, call schedule
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#
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sysc_reschedule:
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larl %r14,sysc_work_loop
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jg schedule # return point is sysc_return
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#
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# _TIF_MCCK_PENDING is set, call handler
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#
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sysc_mcck_pending:
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larl %r14,sysc_work_loop
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jg s390_handle_mcck # TIF bit will be cleared by handler
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#
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# _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal
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#
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sysc_sigpending:
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ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
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la %r2,SP_PTREGS(%r15) # load pt_regs
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brasl %r14,do_signal # call do_signal
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tm __TI_flags+7(%r9),_TIF_RESTART_SVC
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jo sysc_restart
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tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
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jo sysc_singlestep
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j sysc_work_loop
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#
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# _TIF_RESTART_SVC is set, set up registers and restart svc
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#
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sysc_restart:
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ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
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lg %r7,SP_R2(%r15) # load new svc number
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slag %r7,%r7,2 # *4
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mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
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lmg %r2,%r6,SP_R2(%r15) # load svc arguments
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j sysc_do_restart # restart svc
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#
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# _TIF_SINGLE_STEP is set, call do_single_step
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#
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sysc_singlestep:
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ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
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lhi %r0,__LC_PGM_OLD_PSW
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sth %r0,SP_TRAP(%r15) # set trap indication to pgm check
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la %r2,SP_PTREGS(%r15) # address of register-save area
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larl %r14,sysc_return # load adr. of system return
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jg do_single_step # branch to do_sigtrap
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#
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# call syscall_trace before and after system call
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# special linkage: %r12 contains the return address for trace_svc
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#
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sysc_tracesys:
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la %r2,SP_PTREGS(%r15) # load pt_regs
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la %r3,0
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srl %r7,2
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stg %r7,SP_R2(%r15)
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brasl %r14,syscall_trace
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lghi %r0,NR_syscalls
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clg %r0,SP_R2(%r15)
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jnh sysc_tracenogo
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lg %r7,SP_R2(%r15) # strace might have changed the
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sll %r7,2 # system call
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lgf %r8,0(%r7,%r10)
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sysc_tracego:
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lmg %r3,%r6,SP_R3(%r15)
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lg %r2,SP_ORIG_R2(%r15)
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basr %r14,%r8 # call sys_xxx
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stg %r2,SP_R2(%r15) # store return value
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sysc_tracenogo:
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tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
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jz sysc_return
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la %r2,SP_PTREGS(%r15) # load pt_regs
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la %r3,1
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larl %r14,sysc_return # return point is sysc_return
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jg syscall_trace
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#
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# a new process exits the kernel with ret_from_fork
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#
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.globl ret_from_fork
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ret_from_fork:
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lg %r13,__LC_SVC_NEW_PSW+8
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lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
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tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
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jo 0f
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stg %r15,SP_R15(%r15) # store stack pointer for new kthread
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0: brasl %r14,schedule_tail
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stosm 24(%r15),0x03 # reenable interrupts
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j sysc_return
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#
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# clone, fork, vfork, exec and sigreturn need glue,
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# because they all expect pt_regs as parameter,
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# but are called with different parameter.
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# return-address is set up above
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#
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sys_clone_glue:
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la %r2,SP_PTREGS(%r15) # load pt_regs
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jg sys_clone # branch to sys_clone
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#ifdef CONFIG_COMPAT
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sys32_clone_glue:
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la %r2,SP_PTREGS(%r15) # load pt_regs
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jg sys32_clone # branch to sys32_clone
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#endif
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sys_fork_glue:
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la %r2,SP_PTREGS(%r15) # load pt_regs
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jg sys_fork # branch to sys_fork
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sys_vfork_glue:
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la %r2,SP_PTREGS(%r15) # load pt_regs
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jg sys_vfork # branch to sys_vfork
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sys_execve_glue:
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la %r2,SP_PTREGS(%r15) # load pt_regs
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lgr %r12,%r14 # save return address
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brasl %r14,sys_execve # call sys_execve
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ltgr %r2,%r2 # check if execve failed
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bnz 0(%r12) # it did fail -> store result in gpr2
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b 6(%r12) # SKIP STG 2,SP_R2(15) in
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# system_call/sysc_tracesys
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#ifdef CONFIG_COMPAT
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sys32_execve_glue:
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la %r2,SP_PTREGS(%r15) # load pt_regs
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lgr %r12,%r14 # save return address
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brasl %r14,sys32_execve # call sys32_execve
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ltgr %r2,%r2 # check if execve failed
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bnz 0(%r12) # it did fail -> store result in gpr2
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b 6(%r12) # SKIP STG 2,SP_R2(15) in
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# system_call/sysc_tracesys
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#endif
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sys_sigreturn_glue:
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la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
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jg sys_sigreturn # branch to sys_sigreturn
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#ifdef CONFIG_COMPAT
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sys32_sigreturn_glue:
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la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
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jg sys32_sigreturn # branch to sys32_sigreturn
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#endif
|
|
|
|
sys_rt_sigreturn_glue:
|
|
la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
|
|
jg sys_rt_sigreturn # branch to sys_sigreturn
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
sys32_rt_sigreturn_glue:
|
|
la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
|
|
jg sys32_rt_sigreturn # branch to sys32_sigreturn
|
|
#endif
|
|
|
|
sys_sigaltstack_glue:
|
|
la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
|
|
jg sys_sigaltstack # branch to sys_sigreturn
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
sys32_sigaltstack_glue:
|
|
la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
|
|
jg sys32_sigaltstack_wrapper # branch to sys_sigreturn
|
|
#endif
|
|
|
|
/*
|
|
* Program check handler routine
|
|
*/
|
|
|
|
.globl pgm_check_handler
|
|
pgm_check_handler:
|
|
/*
|
|
* First we need to check for a special case:
|
|
* Single stepping an instruction that disables the PER event mask will
|
|
* cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
|
|
* For a single stepped SVC the program check handler gets control after
|
|
* the SVC new PSW has been loaded. But we want to execute the SVC first and
|
|
* then handle the PER event. Therefore we update the SVC old PSW to point
|
|
* to the pgm_check_handler and branch to the SVC handler after we checked
|
|
* if we have to load the kernel stack register.
|
|
* For every other possible cause for PER event without the PER mask set
|
|
* we just ignore the PER event (FIXME: is there anything we have to do
|
|
* for LPSW?).
|
|
*/
|
|
STORE_TIMER __LC_SYNC_ENTER_TIMER
|
|
SAVE_ALL_BASE __LC_SAVE_AREA
|
|
tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
|
|
jnz pgm_per # got per exception -> special case
|
|
SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
|
|
CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
tm SP_PSW+1(%r15),0x01 # interrupting from user ?
|
|
jz pgm_no_vtime
|
|
UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
|
|
UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
|
|
mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
|
|
pgm_no_vtime:
|
|
#endif
|
|
lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
|
|
lgf %r3,__LC_PGM_ILC # load program interruption code
|
|
lghi %r8,0x7f
|
|
ngr %r8,%r3
|
|
pgm_do_call:
|
|
sll %r8,3
|
|
larl %r1,pgm_check_table
|
|
lg %r1,0(%r8,%r1) # load address of handler routine
|
|
la %r2,SP_PTREGS(%r15) # address of register-save area
|
|
larl %r14,sysc_return
|
|
br %r1 # branch to interrupt-handler
|
|
|
|
#
|
|
# handle per exception
|
|
#
|
|
pgm_per:
|
|
tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
|
|
jnz pgm_per_std # ok, normal per event from user space
|
|
# ok its one of the special cases, now we need to find out which one
|
|
clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
|
|
je pgm_svcper
|
|
# no interesting special case, ignore PER event
|
|
lmg %r12,%r15,__LC_SAVE_AREA
|
|
lpswe __LC_PGM_OLD_PSW
|
|
|
|
#
|
|
# Normal per exception
|
|
#
|
|
pgm_per_std:
|
|
SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
|
|
CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
tm SP_PSW+1(%r15),0x01 # interrupting from user ?
|
|
jz pgm_no_vtime2
|
|
UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
|
|
UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
|
|
mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
|
|
pgm_no_vtime2:
|
|
#endif
|
|
lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
|
|
lg %r1,__TI_task(%r9)
|
|
mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
|
|
mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
|
|
mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
|
|
oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
|
|
lgf %r3,__LC_PGM_ILC # load program interruption code
|
|
lghi %r8,0x7f
|
|
ngr %r8,%r3 # clear per-event-bit and ilc
|
|
je sysc_return
|
|
j pgm_do_call
|
|
|
|
#
|
|
# it was a single stepped SVC that is causing all the trouble
|
|
#
|
|
pgm_svcper:
|
|
SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
|
|
CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
tm SP_PSW+1(%r15),0x01 # interrupting from user ?
|
|
jz pgm_no_vtime3
|
|
UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
|
|
UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
|
|
mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
|
|
pgm_no_vtime3:
|
|
#endif
|
|
llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
|
|
lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
|
|
lg %r1,__TI_task(%r9)
|
|
mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
|
|
mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
|
|
mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
|
|
oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
|
|
stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
|
|
j sysc_do_svc
|
|
|
|
/*
|
|
* IO interrupt handler routine
|
|
*/
|
|
.globl io_int_handler
|
|
io_int_handler:
|
|
STORE_TIMER __LC_ASYNC_ENTER_TIMER
|
|
stck __LC_INT_CLOCK
|
|
SAVE_ALL_BASE __LC_SAVE_AREA+32
|
|
SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
|
|
CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
tm SP_PSW+1(%r15),0x01 # interrupting from user ?
|
|
jz io_no_vtime
|
|
UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
|
|
UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
|
|
mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
|
|
io_no_vtime:
|
|
#endif
|
|
lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
|
|
la %r2,SP_PTREGS(%r15) # address of register-save area
|
|
brasl %r14,do_IRQ # call standard irq handler
|
|
|
|
io_return:
|
|
tm SP_PSW+1(%r15),0x01 # returning to user ?
|
|
#ifdef CONFIG_PREEMPT
|
|
jno io_preempt # no -> check for preemptive scheduling
|
|
#else
|
|
jno io_leave # no-> skip resched & signal
|
|
#endif
|
|
tm __TI_flags+7(%r9),_TIF_WORK_INT
|
|
jnz io_work # there is work to do (signals etc.)
|
|
io_leave:
|
|
RESTORE_ALL __LC_RETURN_PSW,0
|
|
io_done:
|
|
|
|
#ifdef CONFIG_PREEMPT
|
|
io_preempt:
|
|
icm %r0,15,__TI_precount(%r9)
|
|
jnz io_leave
|
|
# switch to kernel stack
|
|
lg %r1,SP_R15(%r15)
|
|
aghi %r1,-SP_SIZE
|
|
mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
|
|
xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
|
|
lgr %r15,%r1
|
|
io_resume_loop:
|
|
tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
|
|
jno io_leave
|
|
larl %r1,.Lc_pactive
|
|
mvc __TI_precount(4,%r9),0(%r1)
|
|
stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
|
|
brasl %r14,schedule # call schedule
|
|
stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
|
|
xc __TI_precount(4,%r9),__TI_precount(%r9)
|
|
j io_resume_loop
|
|
#endif
|
|
|
|
#
|
|
# switch to kernel stack, then check TIF bits
|
|
#
|
|
io_work:
|
|
lg %r1,__LC_KERNEL_STACK
|
|
aghi %r1,-SP_SIZE
|
|
mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
|
|
xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
|
|
lgr %r15,%r1
|
|
#
|
|
# One of the work bits is on. Find out which one.
|
|
# Checked are: _TIF_SIGPENDING, _TIF_RESTORE_SIGPENDING, _TIF_NEED_RESCHED
|
|
# and _TIF_MCCK_PENDING
|
|
#
|
|
io_work_loop:
|
|
tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
|
|
jo io_mcck_pending
|
|
tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
|
|
jo io_reschedule
|
|
tm __TI_flags+7(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK)
|
|
jnz io_sigpending
|
|
j io_leave
|
|
|
|
#
|
|
# _TIF_MCCK_PENDING is set, call handler
|
|
#
|
|
io_mcck_pending:
|
|
larl %r14,io_work_loop
|
|
jg s390_handle_mcck # TIF bit will be cleared by handler
|
|
|
|
#
|
|
# _TIF_NEED_RESCHED is set, call schedule
|
|
#
|
|
io_reschedule:
|
|
stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
|
|
brasl %r14,schedule # call scheduler
|
|
stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
|
|
tm __TI_flags+7(%r9),_TIF_WORK_INT
|
|
jz io_leave # there is no work to do
|
|
j io_work_loop
|
|
|
|
#
|
|
# _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal
|
|
#
|
|
io_sigpending:
|
|
stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
|
|
la %r2,SP_PTREGS(%r15) # load pt_regs
|
|
brasl %r14,do_signal # call do_signal
|
|
stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
|
|
j io_work_loop
|
|
|
|
/*
|
|
* External interrupt handler routine
|
|
*/
|
|
.globl ext_int_handler
|
|
ext_int_handler:
|
|
STORE_TIMER __LC_ASYNC_ENTER_TIMER
|
|
stck __LC_INT_CLOCK
|
|
SAVE_ALL_BASE __LC_SAVE_AREA+32
|
|
SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
|
|
CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
tm SP_PSW+1(%r15),0x01 # interrupting from user ?
|
|
jz ext_no_vtime
|
|
UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
|
|
UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
|
|
mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
|
|
ext_no_vtime:
|
|
#endif
|
|
lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
|
|
la %r2,SP_PTREGS(%r15) # address of register-save area
|
|
llgh %r3,__LC_EXT_INT_CODE # get interruption code
|
|
brasl %r14,do_extint
|
|
j io_return
|
|
|
|
__critical_end:
|
|
|
|
/*
|
|
* Machine check handler routines
|
|
*/
|
|
.globl mcck_int_handler
|
|
mcck_int_handler:
|
|
la %r1,4095 # revalidate r1
|
|
spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
|
|
lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
|
|
SAVE_ALL_BASE __LC_SAVE_AREA+64
|
|
la %r12,__LC_MCK_OLD_PSW
|
|
tm __LC_MCCK_CODE,0x80 # system damage?
|
|
jo mcck_int_main # yes -> rest of mcck code invalid
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
la %r14,4095
|
|
mvc __LC_SAVE_AREA+104(8),__LC_ASYNC_ENTER_TIMER
|
|
mvc __LC_ASYNC_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
|
|
tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
|
|
jo 1f
|
|
la %r14,__LC_SYNC_ENTER_TIMER
|
|
clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
|
|
jl 0f
|
|
la %r14,__LC_ASYNC_ENTER_TIMER
|
|
0: clc 0(8,%r14),__LC_EXIT_TIMER
|
|
jl 0f
|
|
la %r14,__LC_EXIT_TIMER
|
|
0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
|
|
jl 0f
|
|
la %r14,__LC_LAST_UPDATE_TIMER
|
|
0: spt 0(%r14)
|
|
mvc __LC_ASYNC_ENTER_TIMER(8),0(%r14)
|
|
1:
|
|
#endif
|
|
tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
|
|
jno mcck_int_main # no -> skip cleanup critical
|
|
tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
|
|
jnz mcck_int_main # from user -> load kernel stack
|
|
clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
|
|
jhe mcck_int_main
|
|
clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
|
|
jl mcck_int_main
|
|
brasl %r14,cleanup_critical
|
|
mcck_int_main:
|
|
lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
|
|
slgr %r14,%r15
|
|
srag %r14,%r14,PAGE_SHIFT
|
|
jz 0f
|
|
lg %r15,__LC_PANIC_STACK # load panic stack
|
|
0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
|
|
jno mcck_no_vtime # no -> no timer update
|
|
tm SP_PSW+1(%r15),0x01 # interrupting from user ?
|
|
jz mcck_no_vtime
|
|
UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
|
|
UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
|
|
mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
|
|
mcck_no_vtime:
|
|
#endif
|
|
lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
|
|
la %r2,SP_PTREGS(%r15) # load pt_regs
|
|
brasl %r14,s390_do_machine_check
|
|
tm SP_PSW+1(%r15),0x01 # returning to user ?
|
|
jno mcck_return
|
|
lg %r1,__LC_KERNEL_STACK # switch to kernel stack
|
|
aghi %r1,-SP_SIZE
|
|
mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
|
|
xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
|
|
lgr %r15,%r1
|
|
stosm __SF_EMPTY(%r15),0x04 # turn dat on
|
|
tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
|
|
jno mcck_return
|
|
brasl %r14,s390_handle_mcck
|
|
mcck_return:
|
|
mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
|
|
ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
|
|
lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
mvc __LC_ASYNC_ENTER_TIMER(8),__LC_SAVE_AREA+104
|
|
tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
|
|
jno 0f
|
|
stpt __LC_EXIT_TIMER
|
|
0:
|
|
#endif
|
|
lpswe __LC_RETURN_MCCK_PSW # back to caller
|
|
|
|
#ifdef CONFIG_SMP
|
|
/*
|
|
* Restart interruption handler, kick starter for additional CPUs
|
|
*/
|
|
.globl restart_int_handler
|
|
restart_int_handler:
|
|
lg %r15,__LC_SAVE_AREA+120 # load ksp
|
|
lghi %r10,__LC_CREGS_SAVE_AREA
|
|
lctlg %c0,%c15,0(%r10) # get new ctl regs
|
|
lghi %r10,__LC_AREGS_SAVE_AREA
|
|
lam %a0,%a15,0(%r10)
|
|
lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
|
|
stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
|
|
jg start_secondary
|
|
#else
|
|
/*
|
|
* If we do not run with SMP enabled, let the new CPU crash ...
|
|
*/
|
|
.globl restart_int_handler
|
|
restart_int_handler:
|
|
basr %r1,0
|
|
restart_base:
|
|
lpswe restart_crash-restart_base(%r1)
|
|
.align 8
|
|
restart_crash:
|
|
.long 0x000a0000,0x00000000,0x00000000,0x00000000
|
|
restart_go:
|
|
#endif
|
|
|
|
#ifdef CONFIG_CHECK_STACK
|
|
/*
|
|
* The synchronous or the asynchronous stack overflowed. We are dead.
|
|
* No need to properly save the registers, we are going to panic anyway.
|
|
* Setup a pt_regs so that show_trace can provide a good call trace.
|
|
*/
|
|
stack_overflow:
|
|
lg %r15,__LC_PANIC_STACK # change to panic stack
|
|
aghi %r1,-SP_SIZE
|
|
mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
|
|
stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
|
|
la %r1,__LC_SAVE_AREA
|
|
chi %r12,__LC_SVC_OLD_PSW
|
|
je 0f
|
|
chi %r12,__LC_PGM_OLD_PSW
|
|
je 0f
|
|
la %r1,__LC_SAVE_AREA+16
|
|
0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
|
|
la %r2,SP_PTREGS(%r15) # load pt_regs
|
|
jg kernel_stack_overflow
|
|
#endif
|
|
|
|
cleanup_table_system_call:
|
|
.quad system_call, sysc_do_svc
|
|
cleanup_table_sysc_return:
|
|
.quad sysc_return, sysc_leave
|
|
cleanup_table_sysc_leave:
|
|
.quad sysc_leave, sysc_work_loop
|
|
cleanup_table_sysc_work_loop:
|
|
.quad sysc_work_loop, sysc_reschedule
|
|
cleanup_table_io_return:
|
|
.quad io_return, io_leave
|
|
cleanup_table_io_leave:
|
|
.quad io_leave, io_done
|
|
cleanup_table_io_work_loop:
|
|
.quad io_work_loop, io_mcck_pending
|
|
|
|
cleanup_critical:
|
|
clc 8(8,%r12),BASED(cleanup_table_system_call)
|
|
jl 0f
|
|
clc 8(8,%r12),BASED(cleanup_table_system_call+8)
|
|
jl cleanup_system_call
|
|
0:
|
|
clc 8(8,%r12),BASED(cleanup_table_sysc_return)
|
|
jl 0f
|
|
clc 8(8,%r12),BASED(cleanup_table_sysc_return+8)
|
|
jl cleanup_sysc_return
|
|
0:
|
|
clc 8(8,%r12),BASED(cleanup_table_sysc_leave)
|
|
jl 0f
|
|
clc 8(8,%r12),BASED(cleanup_table_sysc_leave+8)
|
|
jl cleanup_sysc_leave
|
|
0:
|
|
clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop)
|
|
jl 0f
|
|
clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop+8)
|
|
jl cleanup_sysc_return
|
|
0:
|
|
clc 8(8,%r12),BASED(cleanup_table_io_return)
|
|
jl 0f
|
|
clc 8(8,%r12),BASED(cleanup_table_io_return+8)
|
|
jl cleanup_io_return
|
|
0:
|
|
clc 8(8,%r12),BASED(cleanup_table_io_leave)
|
|
jl 0f
|
|
clc 8(8,%r12),BASED(cleanup_table_io_leave+8)
|
|
jl cleanup_io_leave
|
|
0:
|
|
clc 8(8,%r12),BASED(cleanup_table_io_work_loop)
|
|
jl 0f
|
|
clc 8(8,%r12),BASED(cleanup_table_io_work_loop+8)
|
|
jl cleanup_io_return
|
|
0:
|
|
br %r14
|
|
|
|
cleanup_system_call:
|
|
mvc __LC_RETURN_PSW(16),0(%r12)
|
|
cghi %r12,__LC_MCK_OLD_PSW
|
|
je 0f
|
|
la %r12,__LC_SAVE_AREA+32
|
|
j 1f
|
|
0: la %r12,__LC_SAVE_AREA+64
|
|
1:
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
|
|
jh 0f
|
|
mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
|
|
0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
|
|
jhe cleanup_vtime
|
|
#endif
|
|
clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
|
|
jh 0f
|
|
mvc __LC_SAVE_AREA(32),0(%r12)
|
|
0: stg %r13,8(%r12)
|
|
stg %r12,__LC_SAVE_AREA+96 # argh
|
|
SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
|
|
CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
|
|
lg %r12,__LC_SAVE_AREA+96 # argh
|
|
stg %r15,24(%r12)
|
|
llgh %r7,__LC_SVC_INT_CODE
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
cleanup_vtime:
|
|
clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
|
|
jhe cleanup_stime
|
|
tm SP_PSW+1(%r15),0x01 # interrupting from user ?
|
|
jz cleanup_novtime
|
|
UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
|
|
cleanup_stime:
|
|
clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
|
|
jh cleanup_update
|
|
UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
|
|
cleanup_update:
|
|
mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
|
|
cleanup_novtime:
|
|
#endif
|
|
mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
|
|
la %r12,__LC_RETURN_PSW
|
|
br %r14
|
|
cleanup_system_call_insn:
|
|
.quad sysc_saveall
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
.quad system_call
|
|
.quad sysc_vtime
|
|
.quad sysc_stime
|
|
.quad sysc_update
|
|
#endif
|
|
|
|
cleanup_sysc_return:
|
|
mvc __LC_RETURN_PSW(8),0(%r12)
|
|
mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return)
|
|
la %r12,__LC_RETURN_PSW
|
|
br %r14
|
|
|
|
cleanup_sysc_leave:
|
|
clc 8(8,%r12),BASED(cleanup_sysc_leave_insn)
|
|
je 2f
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
|
|
clc 8(8,%r12),BASED(cleanup_sysc_leave_insn+8)
|
|
je 2f
|
|
#endif
|
|
mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
|
|
cghi %r12,__LC_MCK_OLD_PSW
|
|
jne 0f
|
|
mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
|
|
j 1f
|
|
0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
|
|
1: lmg %r0,%r11,SP_R0(%r15)
|
|
lg %r15,SP_R15(%r15)
|
|
2: la %r12,__LC_RETURN_PSW
|
|
br %r14
|
|
cleanup_sysc_leave_insn:
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
.quad sysc_leave + 16
|
|
#endif
|
|
.quad sysc_leave + 12
|
|
|
|
cleanup_io_return:
|
|
mvc __LC_RETURN_PSW(8),0(%r12)
|
|
mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_work_loop)
|
|
la %r12,__LC_RETURN_PSW
|
|
br %r14
|
|
|
|
cleanup_io_leave:
|
|
clc 8(8,%r12),BASED(cleanup_io_leave_insn)
|
|
je 2f
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
|
|
clc 8(8,%r12),BASED(cleanup_io_leave_insn+8)
|
|
je 2f
|
|
#endif
|
|
mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
|
|
cghi %r12,__LC_MCK_OLD_PSW
|
|
jne 0f
|
|
mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
|
|
j 1f
|
|
0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
|
|
1: lmg %r0,%r11,SP_R0(%r15)
|
|
lg %r15,SP_R15(%r15)
|
|
2: la %r12,__LC_RETURN_PSW
|
|
br %r14
|
|
cleanup_io_leave_insn:
|
|
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
|
.quad io_leave + 20
|
|
#endif
|
|
.quad io_leave + 16
|
|
|
|
/*
|
|
* Integer constants
|
|
*/
|
|
.align 4
|
|
.Lconst:
|
|
.Lc_pactive: .long PREEMPT_ACTIVE
|
|
.Lnr_syscalls: .long NR_syscalls
|
|
.L0x0130: .short 0x130
|
|
.L0x0140: .short 0x140
|
|
.L0x0150: .short 0x150
|
|
.L0x0160: .short 0x160
|
|
.L0x0170: .short 0x170
|
|
.Lcritical_start:
|
|
.quad __critical_start
|
|
.Lcritical_end:
|
|
.quad __critical_end
|
|
|
|
.section .rodata, "a"
|
|
#define SYSCALL(esa,esame,emu) .long esame
|
|
sys_call_table:
|
|
#include "syscalls.S"
|
|
#undef SYSCALL
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
|
|
#define SYSCALL(esa,esame,emu) .long emu
|
|
sys_call_table_emu:
|
|
#include "syscalls.S"
|
|
#undef SYSCALL
|
|
#endif
|