17049d30c2
This patch adds support to use the priority assignment table in the ieee_ets structure to map priorities to traffic classes. Previously ixgbe only supported a 1:1 mapping. Now we can enable and disable hardware DCB support when multiple traffic classes are actually being used. This allows the default case all priorities mapped to traffic class 0 to work in normal hardware mode and utilize the full packet buffer. This patch does not address putting the hardware in 4TC mode so packet buffer space may be underutilized in this case. A follow up patch can address this optimization. But at least we have the hooks to do this now. Also CEE will behave as it always has and map priorities 1:1 with traffic classes. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
133 lines
5.2 KiB
C
133 lines
5.2 KiB
C
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2011 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _DCB_82599_CONFIG_H_
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#define _DCB_82599_CONFIG_H_
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/* DCB register definitions */
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#define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin,
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* 1 WSP - Weighted Strict Priority
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*/
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#define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin,
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* 1 WRR - Weighted Round Robin
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*/
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#define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */
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#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
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#define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */
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#define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must
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* clear!
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*/
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#define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */
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/* Receive UP2TC mapping */
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#define IXGBE_RTRUP2TC_UP_SHIFT 3
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/* Transmit UP2TC mapping */
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#define IXGBE_RTTUP2TC_UP_SHIFT 3
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#define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
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#define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */
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#define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */
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#define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */
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#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet
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* buffers enable
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*/
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#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores
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* (RSS) enable
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*/
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/* RTRPCS Bit Masks */
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#define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */
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/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
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#define IXGBE_RTRPCS_RAC 0x00000004
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#define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */
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/* RTTDT2C Bit Masks */
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#define IXGBE_RTTDT2C_MCL_SHIFT 12
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#define IXGBE_RTTDT2C_BWG_SHIFT 9
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#define IXGBE_RTTDT2C_GSP 0x40000000
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#define IXGBE_RTTDT2C_LSP 0x80000000
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#define IXGBE_RTTPT2C_MCL_SHIFT 12
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#define IXGBE_RTTPT2C_BWG_SHIFT 9
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#define IXGBE_RTTPT2C_GSP 0x40000000
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#define IXGBE_RTTPT2C_LSP 0x80000000
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/* RTTPCS Bit Masks */
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#define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin,
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* 1 SP - Strict Priority
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*/
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#define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */
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#define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */
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#define IXGBE_RTTPCS_ARBD_SHIFT 22
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#define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */
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#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */
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#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
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#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
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#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
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#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
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#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */
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#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */
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/* SECTXMINIFG DCB */
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#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer IFG */
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/* DCB hardware-specific driver APIs */
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/* DCB PFC functions */
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s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en);
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/* DCB hw initialization */
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s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type,
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u8 *prio_tc);
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s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type);
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s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type,
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u8 *prio_tc);
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s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
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u8 rx_pba, u8 pfc_en, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type,
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u8 *prio_tc);
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#endif /* _DCB_82599_CONFIG_H */
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