8263a67e16
This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
190 lines
4.5 KiB
C
190 lines
4.5 KiB
C
/*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2003 - 2007 Paul Mundt
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*
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* ASID handling idea taken from MIPS implementation.
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*/
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#ifndef __ASM_SH_MMU_CONTEXT_H
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#define __ASM_SH_MMU_CONTEXT_H
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#ifdef __KERNEL__
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#include <cpu/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm-generic/mm_hooks.h>
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/*
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* The MMU "context" consists of two things:
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* (a) TLB cache version (or round, cycle whatever expression you like)
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* (b) ASID (Address Space IDentifier)
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*/
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#ifdef CONFIG_CPU_HAS_PTEAEX
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#define MMU_CONTEXT_ASID_MASK 0x0000ffff
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#else
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#define MMU_CONTEXT_ASID_MASK 0x000000ff
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#endif
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#define MMU_CONTEXT_VERSION_MASK (~0UL & ~MMU_CONTEXT_ASID_MASK)
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#define MMU_CONTEXT_FIRST_VERSION (MMU_CONTEXT_ASID_MASK + 1)
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/* Impossible ASID value, to differentiate from NO_CONTEXT. */
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#define MMU_NO_ASID MMU_CONTEXT_FIRST_VERSION
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#define NO_CONTEXT 0UL
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#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
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#ifdef CONFIG_MMU
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#define cpu_context(cpu, mm) ((mm)->context.id[cpu])
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#define cpu_asid(cpu, mm) \
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(cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK)
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/*
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* Virtual Page Number mask
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*/
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#define MMU_VPN_MASK 0xfffff000
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#if defined(CONFIG_SUPERH32)
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#include "mmu_context_32.h"
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#else
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#include "mmu_context_64.h"
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#endif
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/*
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* Get MMU context if needed.
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*/
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static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
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{
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unsigned long asid = asid_cache(cpu);
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/* Check if we have old version of context. */
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if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0)
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/* It's up to date, do nothing */
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return;
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/* It's old, we need to get new context with new version. */
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if (!(++asid & MMU_CONTEXT_ASID_MASK)) {
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/*
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* We exhaust ASID of this version.
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* Flush all TLB and start new cycle.
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*/
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flush_tlb_all();
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#ifdef CONFIG_SUPERH64
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/*
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* The SH-5 cache uses the ASIDs, requiring both the I and D
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* cache to be flushed when the ASID is exhausted. Weak.
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*/
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flush_cache_all();
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#endif
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/*
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* Fix version; Note that we avoid version #0
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* to distingush NO_CONTEXT.
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*/
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if (!asid)
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asid = MMU_CONTEXT_FIRST_VERSION;
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}
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cpu_context(cpu, mm) = asid_cache(cpu) = asid;
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}
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/*
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* Initialize the context related info for a new mm_struct
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* instance.
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*/
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static inline int init_new_context(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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int i;
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for (i = 0; i < num_online_cpus(); i++)
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cpu_context(i, mm) = NO_CONTEXT;
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return 0;
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}
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/*
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* After we have set current->mm to a new value, this activates
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* the context for the new mm so we see the new mappings.
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*/
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static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
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{
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get_mmu_context(mm, cpu);
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set_asid(cpu_asid(cpu, mm));
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}
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static inline void switch_mm(struct mm_struct *prev,
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struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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if (likely(prev != next)) {
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cpu_set(cpu, next->cpu_vm_mask);
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set_TTB(next->pgd);
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activate_context(next, cpu);
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} else
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if (!cpu_test_and_set(cpu, next->cpu_vm_mask))
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activate_context(next, cpu);
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}
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#else
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#define get_mmu_context(mm) do { } while (0)
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#define init_new_context(tsk,mm) (0)
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#define destroy_context(mm) do { } while (0)
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#define set_asid(asid) do { } while (0)
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#define get_asid() (0)
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#define cpu_asid(cpu, mm) ({ (void)cpu; NO_CONTEXT; })
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#define switch_and_save_asid(asid) (0)
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#define set_TTB(pgd) do { } while (0)
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#define get_TTB() (0)
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#define activate_context(mm,cpu) do { } while (0)
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#define switch_mm(prev,next,tsk) do { } while (0)
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#endif /* CONFIG_MMU */
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#define activate_mm(prev, next) switch_mm((prev),(next),NULL)
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define enter_lazy_tlb(mm,tsk) do { } while (0)
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#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
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/*
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* If this processor has an MMU, we need methods to turn it off/on ..
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* paging_init() will also have to be updated for the processor in
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* question.
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*/
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static inline void enable_mmu(void)
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{
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unsigned int cpu = smp_processor_id();
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/* Enable MMU */
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ctrl_outl(MMU_CONTROL_INIT, MMUCR);
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ctrl_barrier();
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if (asid_cache(cpu) == NO_CONTEXT)
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asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION;
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set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK);
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}
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static inline void disable_mmu(void)
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{
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unsigned long cr;
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cr = ctrl_inl(MMUCR);
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cr &= ~MMU_CONTROL_INIT;
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ctrl_outl(cr, MMUCR);
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ctrl_barrier();
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}
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#else
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/*
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* MMU control handlers for processors lacking memory
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* management hardware.
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*/
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#define enable_mmu() do { } while (0)
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#define disable_mmu() do { } while (0)
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#endif
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_MMU_CONTEXT_H */
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