8a3fb8607a
The csp/*.h headers get into the way of multiplatform kernels and are generally not needed anyway. This removes the ones that are completely free of content and moves the other ones to mach/csp/, which already holds a bunch of these. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
227 lines
6.5 KiB
C
227 lines
6.5 KiB
C
/*
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* derived from linux/arch/arm/mach-versatile/core.c
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* linux/arch/arm/mach-bcmring/core.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* Portions copyright Broadcom 2008 */
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/amba/bus.h>
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#include <linux/clkdev.h>
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#include <mach/csp/mm_addr.h>
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#include <mach/hardware.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/timer-sp.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include <mach/cfg_global.h>
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#include "clock.h"
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#include <mach/csp/secHw_def.h>
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#include <mach/csp/chipcHw_inline.h>
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#include <mach/csp/tmrHw_reg.h>
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static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
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static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
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static struct clk pll1_clk = {
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.name = "PLL1",
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.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
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.rate_hz = 2000000000,
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.use_cnt = 7,
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};
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static struct clk uart_clk = {
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.name = "UART",
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.type = CLK_TYPE_PROGRAMMABLE,
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.csp_id = chipcHw_CLOCK_UART,
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.rate_hz = HW_CFG_UART_CLK_HZ,
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.parent = &pll1_clk,
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};
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static struct clk dummy_apb_pclk = {
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.name = "BUSCLK",
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.type = CLK_TYPE_PRIMARY,
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.mode = CLK_MODE_XTAL,
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};
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/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
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#if defined(CONFIG_ARCH_FPGA11107)
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/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
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/* slow down Linux's sense of time */
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#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
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#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
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#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
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#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
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#else
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#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
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#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
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#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
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#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
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#endif
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static struct clk sp804_timer012_clk = {
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.name = "sp804-timer-0,1,2",
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.type = CLK_TYPE_PRIMARY,
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.mode = CLK_MODE_XTAL,
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.rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
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};
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static struct clk sp804_timer3_clk = {
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.name = "sp804-timer-3",
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.type = CLK_TYPE_PRIMARY,
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.mode = CLK_MODE_XTAL,
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.rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
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};
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static struct clk_lookup lookups[] = {
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{ /* Bus clock */
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.con_id = "apb_pclk",
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.clk = &dummy_apb_pclk,
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}, { /* UART0 */
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.dev_id = "uarta",
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.clk = &uart_clk,
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}, { /* UART1 */
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.dev_id = "uartb",
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.clk = &uart_clk,
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}, { /* SP804 timer 0 */
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.dev_id = "sp804",
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.con_id = "timer0",
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.clk = &sp804_timer012_clk,
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}, { /* SP804 timer 1 */
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.dev_id = "sp804",
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.con_id = "timer1",
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.clk = &sp804_timer012_clk,
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}, { /* SP804 timer 3 */
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.dev_id = "sp804",
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.con_id = "timer3",
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.clk = &sp804_timer3_clk,
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}
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};
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static struct amba_device *amba_devs[] __initdata = {
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&uartA_device,
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&uartB_device,
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};
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void __init bcmring_amba_init(void)
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{
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int i;
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u32 bus_clock;
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/* Linux is run initially in non-secure mode. Secure peripherals */
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/* generate FIQ, and must be handled in secure mode. Until we have */
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/* a linux security monitor implementation, keep everything in */
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/* non-secure mode. */
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chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
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secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
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secHw_BLK_MASK_KEY_SCAN |
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secHw_BLK_MASK_TOUCH_SCREEN |
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secHw_BLK_MASK_UART0 |
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secHw_BLK_MASK_UART1 |
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secHw_BLK_MASK_WATCHDOG |
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secHw_BLK_MASK_SPUM |
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secHw_BLK_MASK_DDR2 |
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secHw_BLK_MASK_SPU |
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secHw_BLK_MASK_PKA |
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secHw_BLK_MASK_RNG |
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secHw_BLK_MASK_RTC |
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secHw_BLK_MASK_OTP |
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secHw_BLK_MASK_BOOT |
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secHw_BLK_MASK_MPU |
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secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
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/* Only the devices attached to the AMBA bus are enabled just before the bus is */
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/* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
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/* driver to access these blocks. The bus is probed, and the drivers are loaded. */
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/* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
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bus_clock = chipcHw_REG_BUS_CLOCK_GE
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| chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
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chipcHw_busInterfaceClockEnable(bus_clock);
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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}
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/*
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* Where is the timer (VA)?
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*/
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#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR)
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#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
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#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
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#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
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static int __init bcmring_clocksource_init(void)
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{
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/* setup timer1 as free-running clocksource */
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sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
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/* setup timer3 as free-running clocksource */
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sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
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return 0;
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}
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/*
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* Set up timer interrupt, and return the current time in seconds.
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*/
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void __init bcmring_init_timer(void)
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{
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printk(KERN_INFO "bcmring_init_timer\n");
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/*
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* Initialise to a known state (all timers off)
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*/
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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writel(0, TIMER3_VA_BASE + TIMER_CTRL);
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/*
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* Make irqs happen for the system timer
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*/
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bcmring_clocksource_init();
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sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
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}
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struct sys_timer bcmring_timer = {
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.init = bcmring_init_timer,
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};
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void __init bcmring_init_early(void)
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{
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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}
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