92 lines
3.6 KiB
C
92 lines
3.6 KiB
C
#ifndef _INC_PMCC4_CPLD_H_
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#define _INC_PMCC4_CPLD_H_
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/*-----------------------------------------------------------------------------
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* pmcc4_cpld.h -
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*
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* Copyright (C) 2005 SBE, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* For further information, contact via email: support@sbei.com
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* SBE, Inc. San Ramon, California U.S.A.
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*-----------------------------------------------------------------------------
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*/
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#include <linux/types.h>
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/********************************/
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/* iSPLD control chip registers */
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/********************************/
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#if 0
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#define CPLD_MCSR 0x0
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#define CPLD_MCLK 0x1
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#define CPLD_LEDS 0x2
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#define CPLD_INTR 0x3
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#endif
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struct c4_cpld
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{
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volatile u_int32_t mcsr;/* r/w: Master Clock Source Register */
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volatile u_int32_t mclk;/* r/w: Master Clock Register */
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volatile u_int32_t leds;/* r/w: LED Register */
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volatile u_int32_t intr;/* r: Interrupt Register */
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};
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typedef struct c4_cpld c4cpld_t;
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/* mcsr note: sourcing COMET must be initialized to Master Mode */
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#define PMCC4_CPLD_MCSR_IND 0 /* ports used individual BP Clk as
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* source, no slaves */
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#define PMCC4_CPLD_MCSR_CMT_1 1 /* COMET 1 BP Clk is source, 2,3,4
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* are Clk slaves */
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#define PMCC4_CPLD_MCSR_CMT_2 2 /* COMET 2 BP Clk is source, 1,3,4
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* are Clk slaves */
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#define PMCC4_CPLD_MCSR_CMT_3 3 /* COMET 3 BP Clk is source, 1,2,4
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* are Clk slaves */
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#define PMCC4_CPLD_MCSR_CMT_4 4 /* COMET 4 BP Clk is source, 1,2,3
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* are Clk slaves */
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#define PMCC4_CPLD_MCLK_MASK 0x0f
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#define PMCC4_CPLD_MCLK_P1 0x1
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#define PMCC4_CPLD_MCLK_P2 0x2
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#define PMCC4_CPLD_MCLK_P3 0x4
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#define PMCC4_CPLD_MCLK_P4 0x8
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#define PMCC4_CPLD_MCLK_T1 0x00
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#define PMCC4_CPLD_MCLK_P1_E1 0x01
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#define PMCC4_CPLD_MCLK_P2_E1 0x02
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#define PMCC4_CPLD_MCLK_P3_E1 0x04
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#define PMCC4_CPLD_MCLK_P4_E1 0x08
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#define PMCC4_CPLD_LED_OFF 0
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#define PMCC4_CPLD_LED_ON 1
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#define PMCC4_CPLD_LED_GP0 0x01 /* port 0, green */
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#define PMCC4_CPLD_LED_YP0 0x02 /* port 0, yellow */
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#define PMCC4_CPLD_LED_GP1 0x04 /* port 1, green */
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#define PMCC4_CPLD_LED_YP1 0x08 /* port 1, yellow */
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#define PMCC4_CPLD_LED_GP2 0x10 /* port 2, green */
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#define PMCC4_CPLD_LED_YP2 0x20 /* port 2, yellow */
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#define PMCC4_CPLD_LED_GP3 0x40 /* port 3, green */
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#define PMCC4_CPLD_LED_YP3 0x80 /* port 3, yellow */
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#define PMCC4_CPLD_LED_GREEN (PMCC4_CPLD_LED_GP0 | PMCC4_CPLD_LED_GP1 | \
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PMCC4_CPLD_LED_GP2 | PMCC4_CPLD_LED_GP3 )
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#define PMCC4_CPLD_LED_YELLOW (PMCC4_CPLD_LED_YP0 | PMCC4_CPLD_LED_YP1 | \
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PMCC4_CPLD_LED_YP2 | PMCC4_CPLD_LED_YP3)
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#define PMCC4_CPLD_INTR_MASK 0x0f
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#define PMCC4_CPLD_INTR_CMT_1 0x01
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#define PMCC4_CPLD_INTR_CMT_2 0x02
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#define PMCC4_CPLD_INTR_CMT_3 0x04
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#define PMCC4_CPLD_INTR_CMT_4 0x08
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#endif /* _INC_PMCC4_CPLD_H_ */
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