6000fc4d6f
It is possible for the CPU to re-enable it's interrupt block bit before the write to the interrupt controller has actually masked out the external interupt at the controller. We get around this by reading back from the interrupt controller which will ensure the write has happened. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
83 lines
2.5 KiB
C
83 lines
2.5 KiB
C
/*
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* Interrupt handling for IPR-based IRQ.
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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* Copyright (C) 2006 Paul Mundt
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*
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* Supported system:
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* On-chip supporting modules (TMU, RTC, etc.).
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* On-chip supporting modules for SH7709/SH7709A/SH7729.
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* Hitachi SolutionEngine external I/O:
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* MS7709SE01, MS7709ASE01, and MS7750SE01
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/topology.h>
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static inline struct ipr_desc *get_ipr_desc(unsigned int irq)
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{
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struct irq_chip *chip = get_irq_chip(irq);
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return (void *)((char *)chip - offsetof(struct ipr_desc, chip));
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}
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static void disable_ipr_irq(unsigned int irq)
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{
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struct ipr_data *p = get_irq_chip_data(irq);
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unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
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/* Set the priority in IPR to 0 */
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__raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
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(void)__raw_readw(addr); /* Read back to flush write posting */
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}
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static void enable_ipr_irq(unsigned int irq)
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{
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struct ipr_data *p = get_irq_chip_data(irq);
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unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
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/* Set priority in IPR back to original value */
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__raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
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}
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/*
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* The shift value is now the number of bits to shift, not the number of
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* bits/4. This is to make it easier to read the value directly from the
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* datasheets. The IPR address is calculated using the ipr_offset table.
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*/
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void register_ipr_controller(struct ipr_desc *desc)
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{
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int i;
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desc->chip.mask = disable_ipr_irq;
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desc->chip.unmask = enable_ipr_irq;
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desc->chip.mask_ack = disable_ipr_irq;
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for (i = 0; i < desc->nr_irqs; i++) {
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struct ipr_data *p = desc->ipr_data + i;
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struct irq_desc *irq_desc;
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BUG_ON(p->ipr_idx >= desc->nr_offsets);
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BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
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irq_desc = irq_to_desc_alloc_node(p->irq, numa_node_id());
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if (unlikely(!irq_desc)) {
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printk(KERN_INFO "can not get irq_desc for %d\n",
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p->irq);
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continue;
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}
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disable_irq_nosync(p->irq);
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set_irq_chip_and_handler_name(p->irq, &desc->chip,
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handle_level_irq, "level");
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set_irq_chip_data(p->irq, p);
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disable_ipr_irq(p->irq);
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}
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}
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EXPORT_SYMBOL(register_ipr_controller);
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