87246b7567
For a given SDRAM clock rate, SDRAM chips require memory controllers
to use a specific set of timing minimums and maximums to transfer data
reliably. These parameters can be different for different memory chips
and can also potentially vary by board.
This patch adds the infrastructure for board-*.c files to pass this
timing data to the SDRAM controller init function. The timing data is
specified in an 'omap_sdrc_params' structure, in terms of SDRC
controller register values. An array of these structs, one per SDRC
target clock rate, is passed by the board-*.c file to
omap2_init_common_hw().
This patch does not define the values for different memory chips, nor
does it use the values for anything; those will come in subsequent patches.
linux-omap source commit is bc84ecfc79.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
127 lines
4.3 KiB
C
127 lines
4.3 KiB
C
#ifndef ____ASM_ARCH_SDRC_H
|
|
#define ____ASM_ARCH_SDRC_H
|
|
|
|
/*
|
|
* OMAP2/3 SDRC/SMS register definitions
|
|
*
|
|
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
|
* Copyright (C) 2007-2008 Nokia Corporation
|
|
*
|
|
* Tony Lindgren
|
|
* Paul Walmsley
|
|
* Richard Woodruff
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <mach/io.h>
|
|
|
|
/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
|
|
|
|
#define SDRC_SYSCONFIG 0x010
|
|
#define SDRC_DLLA_CTRL 0x060
|
|
#define SDRC_DLLA_STATUS 0x064
|
|
#define SDRC_DLLB_CTRL 0x068
|
|
#define SDRC_DLLB_STATUS 0x06C
|
|
#define SDRC_POWER 0x070
|
|
#define SDRC_MR_0 0x084
|
|
#define SDRC_ACTIM_CTRL_A_0 0x09c
|
|
#define SDRC_ACTIM_CTRL_B_0 0x0a0
|
|
#define SDRC_RFR_CTRL_0 0x0a4
|
|
|
|
/*
|
|
* These values represent the number of memory clock cycles between
|
|
* autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
|
|
* rows per device, and include a subtraction of a 50 cycle window in the
|
|
* event that the autorefresh command is delayed due to other SDRC activity.
|
|
* The '| 1' sets the ARE field to send one autorefresh when the autorefresh
|
|
* counter reaches 0.
|
|
*
|
|
* These represent optimal values for common parts, it won't work for all.
|
|
* As long as you scale down, most parameters are still work, they just
|
|
* become sub-optimal. The RFR value goes in the opposite direction. If you
|
|
* don't adjust it down as your clock period increases the refresh interval
|
|
* will not be met. Setting all parameters for complete worst case may work,
|
|
* but may cut memory performance by 2x. Due to errata the DLLs need to be
|
|
* unlocked and their value needs run time calibration. A dynamic call is
|
|
* need for that as no single right value exists acorss production samples.
|
|
*
|
|
* Only the FULL speed values are given. Current code is such that rate
|
|
* changes must be made at DPLLoutx2. The actual value adjustment for low
|
|
* frequency operation will be handled by omap_set_performance()
|
|
*
|
|
* By having the boot loader boot up in the fastest L4 speed available likely
|
|
* will result in something which you can switch between.
|
|
*/
|
|
#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
|
|
#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
|
|
#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
|
|
#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
|
|
#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
|
|
|
|
|
|
/*
|
|
* SMS register access
|
|
*/
|
|
|
|
#define OMAP242X_SMS_REGADDR(reg) \
|
|
(void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
|
|
#define OMAP243X_SMS_REGADDR(reg) \
|
|
(void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
|
|
#define OMAP343X_SMS_REGADDR(reg) \
|
|
(void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
|
|
|
|
/* SMS register offsets - read/write with sms_{read,write}_reg() */
|
|
|
|
#define SMS_SYSCONFIG 0x010
|
|
/* REVISIT: fill in other SMS registers here */
|
|
|
|
|
|
#ifndef __ASSEMBLER__
|
|
|
|
/**
|
|
* struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
|
|
* @rate: SDRC clock rate (in Hz)
|
|
* @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
|
|
* @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
|
|
* @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
|
|
* @mr: Value to program to SDRC_MR for this rate
|
|
*
|
|
* This structure holds a pre-computed set of register values for the
|
|
* SDRC for a given SDRC clock rate and SDRAM chip. These are
|
|
* intended to be pre-computed and specified in an array in the board-*.c
|
|
* files. The structure is keyed off the 'rate' field.
|
|
*/
|
|
struct omap_sdrc_params {
|
|
unsigned long rate;
|
|
u32 actim_ctrla;
|
|
u32 actim_ctrlb;
|
|
u32 rfr_ctrl;
|
|
u32 mr;
|
|
};
|
|
|
|
void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
|
|
struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
|
|
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
|
|
struct memory_timings {
|
|
u32 m_type; /* ddr = 1, sdr = 0 */
|
|
u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
|
|
u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
|
|
u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
|
|
u32 base_cs; /* base chip select to use for calculations */
|
|
};
|
|
|
|
extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
|
|
|
|
u32 omap2xxx_sdrc_dll_is_unlocked(void);
|
|
u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
|
|
|
|
#endif /* CONFIG_ARCH_OMAP2 */
|
|
|
|
#endif /* __ASSEMBLER__ */
|
|
|
|
#endif
|