linux/arch/blackfin/lib/ins.S
Michael Hennerich 5c91fb902d Blackfin arch: Add assembly function insl_16
/*
 * CPUs often take a performance hit when accessing unaligned memory
 * locations. The actual performance hit varies, it can be small if the
 * hardware handles it or large if we have to take an exception and fix
 * it
 * in software.
 *
 * Since an ethernet header is 14 bytes network drivers often end up
 * with
 * the IP header at an unaligned offset. The IP header can be aligned by
 * shifting the start of the packet by 2 bytes. Drivers should do this
 * with:
 *
 * skb_reserve(NET_IP_ALIGN);
 *
 * The downside to this alignment of the IP header is that the DMA is
 * now
 * unaligned. On some architectures the cost of an unaligned DMA is high
 * and this cost outweighs the gains made by aligning the IP header.
 *
 * Since this trade off varies between architectures, we allow
 * NET_IP_ALIGN
 * to be overridden.
 */

This new function insl_16 allows to read form 32-bit IO and writes to
16-bit aligned memory. This is useful in above described scenario -
In particular with the AXIS AX88180 Gigabit Ethernet MAC.
Once the device is in 32-bit mode, reads from the RX FIFO always
decrements 4bytes.
While on the other side the destination address in SDRAM is always
16-bit aligned.
If we use skb_reserve(0) the receive buffer is 32-bit aligned but later
we hit a unaligned exception in the IP code.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-11-17 23:46:58 +08:00

98 lines
2.3 KiB
ArmAsm

/*
* File: arch/blackfin/lib/ins.S
* Based on:
* Author: Bas Vermeulen <bas@buyways.nl>
*
* Created: Tue Mar 22 15:27:24 CEST 2005
* Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops.
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
* Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/linkage.h>
#include <asm/blackfin.h>
.align 2
ENTRY(_insl)
P0 = R0; /* P0 = port */
cli R3;
P1 = R1; /* P1 = address */
P2 = R2; /* P2 = count */
SSYNC;
LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
.Llong_loop_s: R0 = [P0];
[P1++] = R0;
NOP;
.Llong_loop_e: NOP;
sti R3;
RTS;
ENDPROC(_insl)
ENTRY(_insw)
P0 = R0; /* P0 = port */
cli R3;
P1 = R1; /* P1 = address */
P2 = R2; /* P2 = count */
SSYNC;
LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
.Lword_loop_s: R0 = W[P0];
W[P1++] = R0;
NOP;
.Lword_loop_e: NOP;
sti R3;
RTS;
ENDPROC(_insw)
ENTRY(_insb)
P0 = R0; /* P0 = port */
cli R3;
P1 = R1; /* P1 = address */
P2 = R2; /* P2 = count */
SSYNC;
LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
.Lbyte_loop_s: R0 = B[P0];
B[P1++] = R0;
NOP;
.Lbyte_loop_e: NOP;
sti R3;
RTS;
ENDPROC(_insb)
ENTRY(_insl_16)
P0 = R0; /* P0 = port */
cli R3;
P1 = R1; /* P1 = address */
P2 = R2; /* P2 = count */
SSYNC;
LSETUP( .Llong16_loop_s, .Llong16_loop_e) LC0 = P2;
.Llong16_loop_s: R0 = [P0];
W[P1++] = R0;
R0 = R0 >> 16;
W[P1++] = R0;
NOP;
.Llong16_loop_e: NOP;
sti R3;
RTS;
ENDPROC(_insl_16)