8ceee660aa
The driver supports the 10Xpress PHY and XFP modules on our reference designs SFE4001 and SFE4002 and the SMC models SMC10GPCIe-XFP and SMC10GPCIe-10BT. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
71 lines
1.6 KiB
C
71 lines
1.6 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2005 Fen Systems Ltd.
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* Copyright 2006 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EFX_SPI_H
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#define EFX_SPI_H
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#include "net_driver.h"
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/**************************************************************************
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*
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* Basic SPI command set and bit definitions
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*
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*************************************************************************/
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/*
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* Commands common to all known devices.
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*
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*/
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/* Write status register */
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#define SPI_WRSR 0x01
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/* Write data to memory array */
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#define SPI_WRITE 0x02
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/* Read data from memory array */
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#define SPI_READ 0x03
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/* Reset write enable latch */
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#define SPI_WRDI 0x04
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/* Read status register */
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#define SPI_RDSR 0x05
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/* Set write enable latch */
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#define SPI_WREN 0x06
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/* SST: Enable write to status register */
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#define SPI_SST_EWSR 0x50
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/*
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* Status register bits. Not all bits are supported on all devices.
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*
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*/
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/* Write-protect pin enabled */
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#define SPI_STATUS_WPEN 0x80
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/* Block protection bit 2 */
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#define SPI_STATUS_BP2 0x10
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/* Block protection bit 1 */
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#define SPI_STATUS_BP1 0x08
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/* Block protection bit 0 */
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#define SPI_STATUS_BP0 0x04
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/* State of the write enable latch */
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#define SPI_STATUS_WEN 0x02
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/* Device busy flag */
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#define SPI_STATUS_NRDY 0x01
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#endif /* EFX_SPI_H */
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