618a2a3a72
Fixes the following error:
ERROR: open brace '{' following enum go on the same line
+enum MFC_SHM_OFS
+{
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
90 lines
2.9 KiB
C
90 lines
2.9 KiB
C
/*
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* linux/drivers/media/video/s5p-mfc/s5p_mfc_shm.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef S5P_MFC_SHM_H_
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#define S5P_MFC_SHM_H_
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enum MFC_SHM_OFS {
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EXTENEDED_DECODE_STATUS = 0x00, /* D */
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SET_FRAME_TAG = 0x04, /* D */
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GET_FRAME_TAG_TOP = 0x08, /* D */
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GET_FRAME_TAG_BOT = 0x0C, /* D */
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PIC_TIME_TOP = 0x10, /* D */
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PIC_TIME_BOT = 0x14, /* D */
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START_BYTE_NUM = 0x18, /* D */
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CROP_INFO_H = 0x20, /* D */
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CROP_INFO_V = 0x24, /* D */
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EXT_ENC_CONTROL = 0x28, /* E */
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ENC_PARAM_CHANGE = 0x2C, /* E */
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RC_VOP_TIMING = 0x30, /* E, MPEG4 */
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HEC_PERIOD = 0x34, /* E, MPEG4 */
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METADATA_ENABLE = 0x38, /* C */
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METADATA_STATUS = 0x3C, /* C */
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METADATA_DISPLAY_INDEX = 0x40, /* C */
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EXT_METADATA_START_ADDR = 0x44, /* C */
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PUT_EXTRADATA = 0x48, /* C */
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EXTRADATA_ADDR = 0x4C, /* C */
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ALLOC_LUMA_DPB_SIZE = 0x64, /* D */
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ALLOC_CHROMA_DPB_SIZE = 0x68, /* D */
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ALLOC_MV_SIZE = 0x6C, /* D */
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P_B_FRAME_QP = 0x70, /* E */
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SAMPLE_ASPECT_RATIO_IDC = 0x74, /* E, H.264, depend on
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ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
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EXTENDED_SAR = 0x78, /* E, H.264, depned on
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ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
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DISP_PIC_PROFILE = 0x7C, /* D */
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FLUSH_CMD_TYPE = 0x80, /* C */
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FLUSH_CMD_INBUF1 = 0x84, /* C */
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FLUSH_CMD_INBUF2 = 0x88, /* C */
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FLUSH_CMD_OUTBUF = 0x8C, /* E */
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NEW_RC_BIT_RATE = 0x90, /* E, format as RC_BIT_RATE(0xC5A8)
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depend on RC_BIT_RATE_CHANGE in ENC_PARAM_CHANGE */
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NEW_RC_FRAME_RATE = 0x94, /* E, format as RC_FRAME_RATE(0xD0D0)
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depend on RC_FRAME_RATE_CHANGE in ENC_PARAM_CHANGE */
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NEW_I_PERIOD = 0x98, /* E, format as I_FRM_CTRL(0xC504)
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depend on I_PERIOD_CHANGE in ENC_PARAM_CHANGE */
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H264_I_PERIOD = 0x9C, /* E, H.264, open GOP */
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RC_CONTROL_CONFIG = 0xA0, /* E */
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BATCH_INPUT_ADDR = 0xA4, /* E */
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BATCH_OUTPUT_ADDR = 0xA8, /* E */
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BATCH_OUTPUT_SIZE = 0xAC, /* E */
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MIN_LUMA_DPB_SIZE = 0xB0, /* D */
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DEVICE_FORMAT_ID = 0xB4, /* C */
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H264_POC_TYPE = 0xB8, /* D */
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MIN_CHROMA_DPB_SIZE = 0xBC, /* D */
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DISP_PIC_FRAME_TYPE = 0xC0, /* D */
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FREE_LUMA_DPB = 0xC4, /* D, VC1 MPEG4 */
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ASPECT_RATIO_INFO = 0xC8, /* D, MPEG4 */
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EXTENDED_PAR = 0xCC, /* D, MPEG4 */
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DBG_HISTORY_INPUT0 = 0xD0, /* C */
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DBG_HISTORY_INPUT1 = 0xD4, /* C */
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DBG_HISTORY_OUTPUT = 0xD8, /* C */
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HIERARCHICAL_P_QP = 0xE0, /* E, H.264 */
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};
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int s5p_mfc_init_shm(struct s5p_mfc_ctx *ctx);
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#define s5p_mfc_write_shm(ctx, x, ofs) \
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do { \
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writel(x, (ctx->shm + ofs)); \
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wmb(); \
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} while (0)
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static inline u32 s5p_mfc_read_shm(struct s5p_mfc_ctx *ctx, unsigned int ofs)
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{
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rmb();
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return readl(ctx->shm + ofs);
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}
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#endif /* S5P_MFC_SHM_H_ */
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