590 lines
14 KiB
C
590 lines
14 KiB
C
/*
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* coretemp.c - Linux kernel module for hardware monitoring
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* Inspired from many hwmon drivers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301 USA.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <linux/hwmon.h>
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#include <linux/sysfs.h>
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#include <linux/hwmon-sysfs.h>
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#include <linux/err.h>
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#include <linux/mutex.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/cpu.h>
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#include <linux/pci.h>
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#include <asm/msr.h>
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#include <asm/processor.h>
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#define DRVNAME "coretemp"
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typedef enum { SHOW_TEMP, SHOW_TJMAX, SHOW_TTARGET, SHOW_LABEL,
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SHOW_NAME } SHOW;
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/*
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* Functions declaration
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*/
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static struct coretemp_data *coretemp_update_device(struct device *dev);
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struct coretemp_data {
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struct device *hwmon_dev;
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struct mutex update_lock;
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const char *name;
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u32 id;
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u16 core_id;
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char valid; /* zero until following fields are valid */
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unsigned long last_updated; /* in jiffies */
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int temp;
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int tjmax;
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int ttarget;
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u8 alarm;
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};
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/*
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* Sysfs stuff
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*/
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static ssize_t show_name(struct device *dev, struct device_attribute
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*devattr, char *buf)
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{
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int ret;
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struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
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struct coretemp_data *data = dev_get_drvdata(dev);
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if (attr->index == SHOW_NAME)
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ret = sprintf(buf, "%s\n", data->name);
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else /* show label */
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ret = sprintf(buf, "Core %d\n", data->core_id);
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return ret;
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}
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static ssize_t show_alarm(struct device *dev, struct device_attribute
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*devattr, char *buf)
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{
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struct coretemp_data *data = coretemp_update_device(dev);
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/* read the Out-of-spec log, never clear */
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return sprintf(buf, "%d\n", data->alarm);
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}
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static ssize_t show_temp(struct device *dev,
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struct device_attribute *devattr, char *buf)
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{
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struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
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struct coretemp_data *data = coretemp_update_device(dev);
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int err;
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if (attr->index == SHOW_TEMP)
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err = data->valid ? sprintf(buf, "%d\n", data->temp) : -EAGAIN;
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else if (attr->index == SHOW_TJMAX)
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err = sprintf(buf, "%d\n", data->tjmax);
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else
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err = sprintf(buf, "%d\n", data->ttarget);
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return err;
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}
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static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL,
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SHOW_TEMP);
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static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, NULL,
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SHOW_TJMAX);
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static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL,
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SHOW_TTARGET);
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static DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL);
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static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_name, NULL, SHOW_LABEL);
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static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, SHOW_NAME);
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static struct attribute *coretemp_attributes[] = {
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&sensor_dev_attr_name.dev_attr.attr,
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&sensor_dev_attr_temp1_label.dev_attr.attr,
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&dev_attr_temp1_crit_alarm.attr,
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&sensor_dev_attr_temp1_input.dev_attr.attr,
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&sensor_dev_attr_temp1_crit.dev_attr.attr,
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NULL
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};
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static const struct attribute_group coretemp_group = {
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.attrs = coretemp_attributes,
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};
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static struct coretemp_data *coretemp_update_device(struct device *dev)
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{
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struct coretemp_data *data = dev_get_drvdata(dev);
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mutex_lock(&data->update_lock);
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if (!data->valid || time_after(jiffies, data->last_updated + HZ)) {
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u32 eax, edx;
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data->valid = 0;
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rdmsr_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
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data->alarm = (eax >> 5) & 1;
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/* update only if data has been valid */
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if (eax & 0x80000000) {
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data->temp = data->tjmax - (((eax >> 16)
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& 0x7f) * 1000);
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data->valid = 1;
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} else {
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dev_dbg(dev, "Temperature data invalid (0x%x)\n", eax);
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}
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data->last_updated = jiffies;
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}
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mutex_unlock(&data->update_lock);
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return data;
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}
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static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
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{
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/* The 100C is default for both mobile and non mobile CPUs */
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int tjmax = 100000;
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int tjmax_ee = 85000;
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int usemsr_ee = 1;
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int err;
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u32 eax, edx;
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struct pci_dev *host_bridge;
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/* Early chips have no MSR for TjMax */
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if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
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usemsr_ee = 0;
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}
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/* Atom CPUs */
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if (c->x86_model == 0x1c) {
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usemsr_ee = 0;
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host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
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if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
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&& (host_bridge->device == 0xa000 /* NM10 based nettop */
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|| host_bridge->device == 0xa010)) /* NM10 based netbook */
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tjmax = 100000;
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else
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tjmax = 90000;
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pci_dev_put(host_bridge);
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}
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if ((c->x86_model > 0xe) && (usemsr_ee)) {
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u8 platform_id;
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/* Now we can detect the mobile CPU using Intel provided table
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http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
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For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
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*/
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err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
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if (err) {
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dev_warn(dev,
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"Unable to access MSR 0x17, assuming desktop"
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" CPU\n");
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usemsr_ee = 0;
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} else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
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/* Trust bit 28 up to Penryn, I could not find any
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documentation on that; if you happen to know
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someone at Intel please ask */
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usemsr_ee = 0;
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} else {
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/* Platform ID bits 52:50 (EDX starts at bit 32) */
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platform_id = (edx >> 18) & 0x7;
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/* Mobile Penryn CPU seems to be platform ID 7 or 5
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(guesswork) */
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if ((c->x86_model == 0x17) &&
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((platform_id == 5) || (platform_id == 7))) {
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/* If MSR EE bit is set, set it to 90 degrees C,
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otherwise 105 degrees C */
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tjmax_ee = 90000;
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tjmax = 105000;
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}
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}
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}
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if (usemsr_ee) {
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err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
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if (err) {
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dev_warn(dev,
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"Unable to access MSR 0xEE, for Tjmax, left"
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" at default\n");
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} else if (eax & 0x40000000) {
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tjmax = tjmax_ee;
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}
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/* if we dont use msr EE it means we are desktop CPU (with exeception
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of Atom) */
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} else if (tjmax == 100000) {
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dev_warn(dev, "Using relative temperature scale!\n");
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}
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return tjmax;
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}
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static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
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struct device *dev)
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{
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/* The 100C is default for both mobile and non mobile CPUs */
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int err;
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u32 eax, edx;
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u32 val;
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/* A new feature of current Intel(R) processors, the
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IA32_TEMPERATURE_TARGET contains the TjMax value */
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err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
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if (err) {
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dev_warn(dev, "Unable to read TjMax from CPU.\n");
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} else {
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val = (eax >> 16) & 0xff;
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/*
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* If the TjMax is not plausible, an assumption
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* will be used
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*/
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if ((val > 80) && (val < 120)) {
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dev_info(dev, "TjMax is %d C.\n", val);
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return val * 1000;
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}
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}
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/*
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* An assumption is made for early CPUs and unreadable MSR.
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* NOTE: the given value may not be correct.
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*/
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switch (c->x86_model) {
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case 0xe:
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case 0xf:
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case 0x16:
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case 0x1a:
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dev_warn(dev, "TjMax is assumed as 100 C!\n");
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return 100000;
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break;
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case 0x17:
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case 0x1c: /* Atom CPUs */
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return adjust_tjmax(c, id, dev);
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break;
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default:
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dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
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" using default TjMax of 100C.\n", c->x86_model);
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return 100000;
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}
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}
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static int __devinit coretemp_probe(struct platform_device *pdev)
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{
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struct coretemp_data *data;
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struct cpuinfo_x86 *c = &cpu_data(pdev->id);
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int err;
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u32 eax, edx;
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if (!(data = kzalloc(sizeof(struct coretemp_data), GFP_KERNEL))) {
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err = -ENOMEM;
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dev_err(&pdev->dev, "Out of memory\n");
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goto exit;
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}
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data->id = pdev->id;
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#ifdef CONFIG_SMP
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data->core_id = c->cpu_core_id;
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#endif
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data->name = "coretemp";
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mutex_init(&data->update_lock);
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/* test if we can access the THERM_STATUS MSR */
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err = rdmsr_safe_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
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if (err) {
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dev_err(&pdev->dev,
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"Unable to access THERM_STATUS MSR, giving up\n");
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goto exit_free;
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}
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/* Check if we have problem with errata AE18 of Core processors:
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Readings might stop update when processor visited too deep sleep,
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fixed for stepping D0 (6EC).
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*/
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if ((c->x86_model == 0xe) && (c->x86_mask < 0xc)) {
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/* check for microcode update */
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rdmsr_on_cpu(data->id, MSR_IA32_UCODE_REV, &eax, &edx);
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if (edx < 0x39) {
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err = -ENODEV;
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dev_err(&pdev->dev,
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"Errata AE18 not fixed, update BIOS or "
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"microcode of the CPU!\n");
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goto exit_free;
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}
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}
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data->tjmax = get_tjmax(c, data->id, &pdev->dev);
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platform_set_drvdata(pdev, data);
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/*
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* read the still undocumented IA32_TEMPERATURE_TARGET. It exists
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* on older CPUs but not in this register,
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* Atoms don't have it either.
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*/
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if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
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err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
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&eax, &edx);
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if (err) {
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dev_warn(&pdev->dev, "Unable to read"
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" IA32_TEMPERATURE_TARGET MSR\n");
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} else {
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data->ttarget = data->tjmax -
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(((eax >> 8) & 0xff) * 1000);
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err = device_create_file(&pdev->dev,
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&sensor_dev_attr_temp1_max.dev_attr);
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if (err)
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goto exit_free;
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}
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}
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if ((err = sysfs_create_group(&pdev->dev.kobj, &coretemp_group)))
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goto exit_dev;
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data->hwmon_dev = hwmon_device_register(&pdev->dev);
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if (IS_ERR(data->hwmon_dev)) {
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err = PTR_ERR(data->hwmon_dev);
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dev_err(&pdev->dev, "Class registration failed (%d)\n",
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err);
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goto exit_class;
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}
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return 0;
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exit_class:
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sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
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exit_dev:
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device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
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exit_free:
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kfree(data);
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exit:
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return err;
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}
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static int __devexit coretemp_remove(struct platform_device *pdev)
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{
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struct coretemp_data *data = platform_get_drvdata(pdev);
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hwmon_device_unregister(data->hwmon_dev);
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sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
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device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
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platform_set_drvdata(pdev, NULL);
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kfree(data);
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return 0;
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}
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static struct platform_driver coretemp_driver = {
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.driver = {
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.owner = THIS_MODULE,
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.name = DRVNAME,
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},
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.probe = coretemp_probe,
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.remove = __devexit_p(coretemp_remove),
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};
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struct pdev_entry {
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struct list_head list;
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struct platform_device *pdev;
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unsigned int cpu;
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#ifdef CONFIG_SMP
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u16 phys_proc_id;
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u16 cpu_core_id;
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#endif
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};
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static LIST_HEAD(pdev_list);
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static DEFINE_MUTEX(pdev_list_mutex);
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static int __cpuinit coretemp_device_add(unsigned int cpu)
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{
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int err;
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struct platform_device *pdev;
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struct pdev_entry *pdev_entry;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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/*
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* CPUID.06H.EAX[0] indicates whether the CPU has thermal
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* sensors. We check this bit only, all the early CPUs
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* without thermal sensors will be filtered out.
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*/
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if (!cpu_has(c, X86_FEATURE_DTS)) {
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printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
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" has no thermal sensor.\n", c->x86_model);
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return 0;
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}
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mutex_lock(&pdev_list_mutex);
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#ifdef CONFIG_SMP
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/* Skip second HT entry of each core */
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list_for_each_entry(pdev_entry, &pdev_list, list) {
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if (c->phys_proc_id == pdev_entry->phys_proc_id &&
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c->cpu_core_id == pdev_entry->cpu_core_id) {
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err = 0; /* Not an error */
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goto exit;
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}
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}
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#endif
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pdev = platform_device_alloc(DRVNAME, cpu);
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if (!pdev) {
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err = -ENOMEM;
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printk(KERN_ERR DRVNAME ": Device allocation failed\n");
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goto exit;
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}
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pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL);
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if (!pdev_entry) {
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err = -ENOMEM;
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goto exit_device_put;
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}
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err = platform_device_add(pdev);
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if (err) {
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printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
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err);
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goto exit_device_free;
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}
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pdev_entry->pdev = pdev;
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pdev_entry->cpu = cpu;
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#ifdef CONFIG_SMP
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pdev_entry->phys_proc_id = c->phys_proc_id;
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pdev_entry->cpu_core_id = c->cpu_core_id;
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#endif
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list_add_tail(&pdev_entry->list, &pdev_list);
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mutex_unlock(&pdev_list_mutex);
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return 0;
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exit_device_free:
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kfree(pdev_entry);
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exit_device_put:
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platform_device_put(pdev);
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exit:
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mutex_unlock(&pdev_list_mutex);
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return err;
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}
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static void coretemp_device_remove(unsigned int cpu)
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{
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struct pdev_entry *p;
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unsigned int i;
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mutex_lock(&pdev_list_mutex);
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list_for_each_entry(p, &pdev_list, list) {
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if (p->cpu != cpu)
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continue;
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platform_device_unregister(p->pdev);
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list_del(&p->list);
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mutex_unlock(&pdev_list_mutex);
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kfree(p);
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for_each_cpu(i, cpu_sibling_mask(cpu))
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if (i != cpu && !coretemp_device_add(i))
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break;
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return;
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}
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mutex_unlock(&pdev_list_mutex);
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}
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static int __cpuinit coretemp_cpu_callback(struct notifier_block *nfb,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
unsigned int cpu = (unsigned long) hcpu;
|
|
|
|
switch (action) {
|
|
case CPU_ONLINE:
|
|
case CPU_DOWN_FAILED:
|
|
coretemp_device_add(cpu);
|
|
break;
|
|
case CPU_DOWN_PREPARE:
|
|
coretemp_device_remove(cpu);
|
|
break;
|
|
}
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block coretemp_cpu_notifier __refdata = {
|
|
.notifier_call = coretemp_cpu_callback,
|
|
};
|
|
|
|
static int __init coretemp_init(void)
|
|
{
|
|
int i, err = -ENODEV;
|
|
|
|
/* quick check if we run Intel */
|
|
if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
|
|
goto exit;
|
|
|
|
err = platform_driver_register(&coretemp_driver);
|
|
if (err)
|
|
goto exit;
|
|
|
|
for_each_online_cpu(i)
|
|
coretemp_device_add(i);
|
|
|
|
#ifndef CONFIG_HOTPLUG_CPU
|
|
if (list_empty(&pdev_list)) {
|
|
err = -ENODEV;
|
|
goto exit_driver_unreg;
|
|
}
|
|
#endif
|
|
|
|
register_hotcpu_notifier(&coretemp_cpu_notifier);
|
|
return 0;
|
|
|
|
#ifndef CONFIG_HOTPLUG_CPU
|
|
exit_driver_unreg:
|
|
platform_driver_unregister(&coretemp_driver);
|
|
#endif
|
|
exit:
|
|
return err;
|
|
}
|
|
|
|
static void __exit coretemp_exit(void)
|
|
{
|
|
struct pdev_entry *p, *n;
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
unregister_hotcpu_notifier(&coretemp_cpu_notifier);
|
|
#endif
|
|
mutex_lock(&pdev_list_mutex);
|
|
list_for_each_entry_safe(p, n, &pdev_list, list) {
|
|
platform_device_unregister(p->pdev);
|
|
list_del(&p->list);
|
|
kfree(p);
|
|
}
|
|
mutex_unlock(&pdev_list_mutex);
|
|
platform_driver_unregister(&coretemp_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
|
|
MODULE_DESCRIPTION("Intel Core temperature monitor");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
module_init(coretemp_init)
|
|
module_exit(coretemp_exit)
|