1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
119 lines
5.2 KiB
C
119 lines
5.2 KiB
C
/****************************************************************************/
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/*
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* linux/include/asm-arm/arch-l7200/sib.h
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*
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* Registers and helper functions for the Serial Interface Bus.
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*
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* (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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/****************************************************************************/
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#define SIB_OFF 0x00040000 /* Offset from IO_START to the SIB reg's. */
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/* IO_START and IO_BASE are defined in hardware.h */
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#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
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#define SIB_BASE (IO_BASE + SIB_OFF) /* Virtual addr of the SIB reg. */
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/* Offsets from the start of the SIB for all the registers. */
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/* Define the SIB registers for use by device drivers and the kernel. */
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typedef struct
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{
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unsigned int MCCR; /* SIB Control Register Offset: 0x00 */
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unsigned int RES1; /* Reserved Offset: 0x04 */
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unsigned int MCDR0; /* SIB Data Register 0 Offset: 0x08 */
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unsigned int MCDR1; /* SIB Data Register 1 Offset: 0x0c */
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unsigned int MCDR2; /* SIB Data Register 2 (UCB1x00) Offset: 0x10 */
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unsigned int RES2; /* Reserved Offset: 0x14 */
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unsigned int MCSR; /* SIB Status Register Offset: 0x18 */
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} SIB_Interface;
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#define SIB ((volatile SIB_Interface *) (SIB_BASE))
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/* MCCR */
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#define INTERNAL_FREQ 9216000 /* Hertz */
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#define AUDIO_FREQ 5000 /* Hertz */
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#define TELECOM_FREQ 5000 /* Hertz */
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#define AUDIO_DIVIDE (INTERNAL_FREQ / (32 * AUDIO_FREQ))
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#define TELECOM_DIVIDE (INTERNAL_FREQ / (32 * TELECOM_FREQ))
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#define MCCR_ASD57 AUDIO_DIVIDE
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#define MCCR_TSD57 (TELECOM_DIVIDE << 8)
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#define MCCR_MCE (1 << 16) /* SIB enable */
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#define MCCR_ECS (1 << 17) /* External Clock Select */
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#define MCCR_ADM (1 << 18) /* A/D Data Sampling */
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#define MCCR_PMC (1 << 26) /* PIN Multiplexer Control */
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#define GET_ASD ((SIB->MCCR >> 0) & 0x3f) /* Audio Sample Rate Div. */
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#define GET_TSD ((SIB->MCCR >> 8) & 0x3f) /* Telcom Sample Rate Div. */
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#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
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#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
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#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
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#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */
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#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
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#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */
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#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
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#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
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#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
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#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
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#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
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#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
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/* MCDR0 */
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#define AUDIO_RECV ((SIB->MCDR0 >> 4) & 0xfff)
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#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
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/* MCDR1 */
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#define TELECOM_RECV ((SIB->MCDR1 >> 2) & 032fff)
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#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
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/* MCSR */
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#define MCSR_ATU (1 << 4) /* Audio Transmit FIFO Underrun */
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#define MCSR_ARO (1 << 5) /* Audio Receive FIFO Underrun */
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#define MCSR_TTU (1 << 6) /* TELECOM Transmit FIFO Underrun */
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#define MCSR_TRO (1 << 7) /* TELECOM Receive FIFO Underrun */
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#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
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#define GET_ATS ((SIB->MCSR >> 0) & 0x01) /* Audio Transmit FIFO Service Req*/
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#define GET_ARS ((SIB->MCSR >> 1) & 0x01) /* Audio Recv FIFO Service Request*/
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#define GET_TTS ((SIB->MCSR >> 2) & 0x01) /* TELECOM Transmit FIFO Flag */
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#define GET_TRS ((SIB->MCSR >> 3) & 0x01) /* TELECOM Recv FIFO Service Req. */
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#define GET_ATU ((SIB->MCSR >> 4) & 0x01) /* Audio Transmit FIFO Underrun */
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#define GET_ARO ((SIB->MCSR >> 5) & 0x01) /* Audio Receive FIFO Underrun */
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#define GET_TTU ((SIB->MCSR >> 6) & 0x01) /* TELECOM Transmit FIFO Underrun */
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#define GET_TRO ((SIB->MCSR >> 7) & 0x01) /* TELECOM Receive FIFO Underrun */
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#define GET_ANF ((SIB->MCSR >> 8) & 0x01) /* Audio Transmit FIFO not full */
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#define GET_ANE ((SIB->MCSR >> 9) & 0x01) /* Audio Receive FIFO not empty */
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#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
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#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
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#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
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#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
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#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
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#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
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/* MCDR2 */
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#define MCDR2_rW (1 << 16)
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#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
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#define MCDR2_WRITE_COMPLETE GET_CWC
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#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
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#define MCDR2_READ_COMPLETE GET_CRC
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#define MCDR2_READ (SIB->MCDR2 & 0xffff)
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