74a01180db
This patch fixes a null pointer exception caused by removal of 'ack()' for level interrupts in the Xilinx interrupt driver. A recent change to the xilinx interrupt controller removed the ack hook for level irqs. Signed-off-by: Roderick Colenbrander <thunderbird2k@gmail.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
298 lines
7.8 KiB
C
298 lines
7.8 KiB
C
/*
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* Interrupt controller driver for Xilinx Virtex FPGAs
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*
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* Copyright (C) 2007 Secret Lab Technologies Ltd.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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/*
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* This is a driver for the interrupt controller typically found in
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* Xilinx Virtex FPGA designs.
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*
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* The interrupt sense levels are hard coded into the FPGA design with
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* typically a 1:1 relationship between irq lines and devices (no shared
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* irq lines). Therefore, this driver does not attempt to handle edge
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* and level interrupts differently.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/i8259.h>
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#include <asm/irq.h>
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/*
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* INTC Registers
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*/
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#define XINTC_ISR 0 /* Interrupt Status */
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#define XINTC_IPR 4 /* Interrupt Pending */
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#define XINTC_IER 8 /* Interrupt Enable */
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#define XINTC_IAR 12 /* Interrupt Acknowledge */
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#define XINTC_SIE 16 /* Set Interrupt Enable bits */
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#define XINTC_CIE 20 /* Clear Interrupt Enable bits */
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#define XINTC_IVR 24 /* Interrupt Vector */
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#define XINTC_MER 28 /* Master Enable */
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static struct irq_host *master_irqhost;
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#define XILINX_INTC_MAXIRQS (32)
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/* The following table allows the interrupt type, edge or level,
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* to be cached after being read from the device tree until the interrupt
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* is mapped
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*/
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static int xilinx_intc_typetable[XILINX_INTC_MAXIRQS];
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/* Map the interrupt type from the device tree to the interrupt types
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* used by the interrupt subsystem
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*/
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static unsigned char xilinx_intc_map_senses[] = {
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IRQ_TYPE_EDGE_RISING,
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IRQ_TYPE_EDGE_FALLING,
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IRQ_TYPE_LEVEL_HIGH,
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IRQ_TYPE_LEVEL_LOW,
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};
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/*
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* The interrupt controller is setup such that it doesn't work well with
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* the level interrupt handler in the kernel because the handler acks the
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* interrupt before calling the application interrupt handler. To deal with
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* that, we use 2 different irq chips so that different functions can be
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* used for level and edge type interrupts.
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*
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* IRQ Chip common (across level and edge) operations
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*/
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static void xilinx_intc_mask(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void * regs = get_irq_chip_data(virq);
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pr_debug("mask: %d\n", irq);
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out_be32(regs + XINTC_CIE, 1 << irq);
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}
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static int xilinx_intc_set_type(unsigned int virq, unsigned int flow_type)
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{
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struct irq_desc *desc = get_irq_desc(virq);
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desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
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desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
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if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
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desc->status |= IRQ_LEVEL;
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return 0;
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}
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/*
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* IRQ Chip level operations
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*/
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static void xilinx_intc_level_unmask(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void * regs = get_irq_chip_data(virq);
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pr_debug("unmask: %d\n", irq);
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out_be32(regs + XINTC_SIE, 1 << irq);
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/* ack level irqs because they can't be acked during
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* ack function since the handle_level_irq function
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* acks the irq before calling the inerrupt handler
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*/
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out_be32(regs + XINTC_IAR, 1 << irq);
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}
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static struct irq_chip xilinx_intc_level_irqchip = {
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.typename = "Xilinx Level INTC",
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.mask = xilinx_intc_mask,
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.mask_ack = xilinx_intc_mask,
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.unmask = xilinx_intc_level_unmask,
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.set_type = xilinx_intc_set_type,
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};
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/*
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* IRQ Chip edge operations
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*/
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static void xilinx_intc_edge_unmask(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void *regs = get_irq_chip_data(virq);
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pr_debug("unmask: %d\n", irq);
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out_be32(regs + XINTC_SIE, 1 << irq);
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}
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static void xilinx_intc_edge_ack(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void * regs = get_irq_chip_data(virq);
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pr_debug("ack: %d\n", irq);
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out_be32(regs + XINTC_IAR, 1 << irq);
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}
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static struct irq_chip xilinx_intc_edge_irqchip = {
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.typename = "Xilinx Edge INTC",
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.mask = xilinx_intc_mask,
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.unmask = xilinx_intc_edge_unmask,
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.ack = xilinx_intc_edge_ack,
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.set_type = xilinx_intc_set_type,
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};
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/*
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* IRQ Host operations
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*/
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/**
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* xilinx_intc_xlate - translate virq# from device tree interrupts property
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*/
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static int xilinx_intc_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_flags)
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{
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if ((intsize < 2) || (intspec[0] >= XILINX_INTC_MAXIRQS))
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return -EINVAL;
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/* keep a copy of the interrupt type til the interrupt is mapped
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*/
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xilinx_intc_typetable[intspec[0]] = xilinx_intc_map_senses[intspec[1]];
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/* Xilinx uses 2 interrupt entries, the 1st being the h/w
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* interrupt number, the 2nd being the interrupt type, edge or level
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*/
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*out_hwirq = intspec[0];
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*out_flags = xilinx_intc_map_senses[intspec[1]];
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return 0;
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}
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static int xilinx_intc_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t irq)
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{
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set_irq_chip_data(virq, h->host_data);
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if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH ||
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xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) {
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set_irq_chip_and_handler(virq, &xilinx_intc_level_irqchip,
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handle_level_irq);
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} else {
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set_irq_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
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handle_edge_irq);
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}
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return 0;
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}
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static struct irq_host_ops xilinx_intc_ops = {
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.map = xilinx_intc_map,
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.xlate = xilinx_intc_xlate,
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};
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struct irq_host * __init
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xilinx_intc_init(struct device_node *np)
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{
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struct irq_host * irq;
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void * regs;
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/* Find and map the intc registers */
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regs = of_iomap(np, 0);
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if (!regs) {
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pr_err("xilinx_intc: could not map registers\n");
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return NULL;
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}
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/* Setup interrupt controller */
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out_be32(regs + XINTC_IER, 0); /* disable all irqs */
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out_be32(regs + XINTC_IAR, ~(u32) 0); /* Acknowledge pending irqs */
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out_be32(regs + XINTC_MER, 0x3UL); /* Turn on the Master Enable. */
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/* Allocate and initialize an irq_host structure. */
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irq = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, XILINX_INTC_MAXIRQS,
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&xilinx_intc_ops, -1);
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if (!irq)
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panic(__FILE__ ": Cannot allocate IRQ host\n");
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irq->host_data = regs;
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return irq;
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}
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int xilinx_intc_get_irq(void)
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{
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void * regs = master_irqhost->host_data;
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pr_debug("get_irq:\n");
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return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR));
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}
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#if defined(CONFIG_PPC_I8259)
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/*
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* Support code for cascading to 8259 interrupt controllers
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*/
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static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int cascade_irq = i8259_irq();
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if (cascade_irq)
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generic_handle_irq(cascade_irq);
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/* Let xilinx_intc end the interrupt */
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desc->chip->unmask(irq);
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}
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static void __init xilinx_i8259_setup_cascade(void)
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{
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struct device_node *cascade_node;
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int cascade_irq;
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/* Initialize i8259 controller */
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cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
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if (!cascade_node)
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return;
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cascade_irq = irq_of_parse_and_map(cascade_node, 0);
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if (!cascade_irq) {
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pr_err("virtex_ml510: Failed to map cascade interrupt\n");
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goto out;
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}
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i8259_init(cascade_node, 0);
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set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
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/* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
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/* This looks like a dirty hack to me --gcl */
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outb(0xc0, 0x4d0);
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outb(0xc0, 0x4d1);
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out:
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of_node_put(cascade_node);
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}
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#else
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static inline void xilinx_i8259_setup_cascade(void) { return; }
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#endif /* defined(CONFIG_PPC_I8259) */
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static struct of_device_id xilinx_intc_match[] __initconst = {
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{ .compatible = "xlnx,opb-intc-1.00.c", },
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{ .compatible = "xlnx,xps-intc-1.00.a", },
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{}
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};
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/*
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* Initialize master Xilinx interrupt controller
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*/
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void __init xilinx_intc_init_tree(void)
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{
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struct device_node *np;
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/* find top level interrupt controller */
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for_each_matching_node(np, xilinx_intc_match) {
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if (!of_get_property(np, "interrupts", NULL))
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break;
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}
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BUG_ON(!np);
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master_irqhost = xilinx_intc_init(np);
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BUG_ON(!master_irqhost);
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irq_set_default_host(master_irqhost);
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of_node_put(np);
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xilinx_i8259_setup_cascade();
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}
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