cbb2c9617a
Add support for SATA controller on the DA850/OMAP-L138/AM18x devices. The patch adds the necessary clocks, platform resources and a routine to initialize the SATA controller. The PHY configuration in this patch is courtesy the work done by Zegeye Alemu, Swaminathan and Mansoor Ahamed from TI. While testing this patch, enable port multiplier support iff you are actually using one. The reasons of this behaviour are discussed here: http://patchwork.ozlabs.org/patch/78163/ ChangeLog: v3: Removed fields which were being initialized to zero in PHY configuration. Moved SATA base address definition to the top of the file to make it inline with what is done for the rest of the modules. v2: Addressed comments from Sergei. Removed unnecessary braces and removed unnecessary else after goto. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
132 lines
4.7 KiB
C
132 lines
4.7 KiB
C
/*
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* Chip specific defines for DA8XX/OMAP L1XX SoC
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
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#define __ASM_ARCH_DAVINCI_DA8XX_H
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#include <video/da8xx-fb.h>
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#include <linux/platform_device.h>
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#include <linux/davinci_emac.h>
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#include <linux/spi/spi.h>
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#include <mach/serial.h>
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#include <mach/edma.h>
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#include <mach/i2c.h>
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#include <mach/asp.h>
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#include <mach/mmc.h>
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#include <mach/usb.h>
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#include <mach/pm.h>
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#include <mach/spi.h>
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extern void __iomem *da8xx_syscfg0_base;
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extern void __iomem *da8xx_syscfg1_base;
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/*
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* If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
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* (than the regular 300Mhz variant), the board code should set this up
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* with the supported speed before calling da850_register_cpufreq().
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*/
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extern unsigned int da850_max_speed;
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/*
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* The cp_intc interrupt controller for the da8xx isn't in the same
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* chunk of physical memory space as the other registers (like it is
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* on the davincis) so it needs to be mapped separately. It will be
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* mapped early on when the I/O space is mapped and we'll put it just
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* before the I/O space in the processor's virtual memory space.
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*/
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#define DA8XX_CP_INTC_BASE 0xfffee000
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#define DA8XX_CP_INTC_SIZE SZ_8K
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#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
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#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
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#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
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#define DA8XX_JTAG_ID_REG 0x18
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#define DA8XX_CFGCHIP0_REG 0x17c
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#define DA8XX_CFGCHIP2_REG 0x184
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#define DA8XX_CFGCHIP3_REG 0x188
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#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
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#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
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#define DA8XX_DEEPSLEEP_REG 0x8
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#define DA8XX_PWRDN_REG 0x18
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#define DA8XX_PSC0_BASE 0x01c10000
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#define DA8XX_PLL0_BASE 0x01c11000
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#define DA8XX_TIMER64P0_BASE 0x01c20000
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#define DA8XX_TIMER64P1_BASE 0x01c21000
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#define DA8XX_GPIO_BASE 0x01e26000
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#define DA8XX_PSC1_BASE 0x01e27000
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#define DA8XX_AEMIF_CS2_BASE 0x60000000
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#define DA8XX_AEMIF_CS3_BASE 0x62000000
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#define DA8XX_AEMIF_CTL_BASE 0x68000000
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#define DA8XX_ARM_RAM_BASE 0xffff0000
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void __init da830_init(void);
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void __init da850_init(void);
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int da830_register_edma(struct edma_rsv_info *rsv);
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int da850_register_edma(struct edma_rsv_info *rsv[2]);
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int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
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int da8xx_register_spi(int instance, struct spi_board_info *info, unsigned len);
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int da8xx_register_watchdog(void);
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int da8xx_register_usb20(unsigned mA, unsigned potpgt);
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int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
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int da8xx_register_emac(void);
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int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
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int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
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int da850_register_mmcsd1(struct davinci_mmc_config *config);
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void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
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int da8xx_register_rtc(void);
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int da850_register_cpufreq(char *async_clk);
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int da8xx_register_cpuidle(void);
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void __iomem * __init da8xx_get_mem_ctlr(void);
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int da850_register_pm(struct platform_device *pdev);
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int __init da850_register_sata(unsigned long refclkpn);
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extern struct platform_device da8xx_serial_device;
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extern struct emac_platform_data da8xx_emac_pdata;
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extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
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extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
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extern struct davinci_spi_platform_data da8xx_spi_pdata[];
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extern struct platform_device da8xx_wdt_device;
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extern const short da830_emif25_pins[];
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extern const short da830_spi0_pins[];
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extern const short da830_spi1_pins[];
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extern const short da830_mmc_sd_pins[];
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extern const short da830_uart0_pins[];
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extern const short da830_uart1_pins[];
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extern const short da830_uart2_pins[];
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extern const short da830_usb20_pins[];
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extern const short da830_usb11_pins[];
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extern const short da830_uhpi_pins[];
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extern const short da830_cpgmac_pins[];
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extern const short da830_emif3c_pins[];
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extern const short da830_mcasp0_pins[];
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extern const short da830_mcasp1_pins[];
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extern const short da830_mcasp2_pins[];
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extern const short da830_i2c0_pins[];
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extern const short da830_i2c1_pins[];
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extern const short da830_lcdcntl_pins[];
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extern const short da830_pwm_pins[];
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extern const short da830_ecap0_pins[];
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extern const short da830_ecap1_pins[];
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extern const short da830_ecap2_pins[];
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extern const short da830_eqep0_pins[];
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extern const short da830_eqep1_pins[];
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extern const short da850_i2c0_pins[];
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extern const short da850_i2c1_pins[];
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extern const short da850_lcdcntl_pins[];
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#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
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