775c7742ad
- Introduced IOC poll mechanism which replaces current interrupt
based FW READY method.
- The timer based poll routine in IOC will query the ioc_fwstate
register to see if there is a state change in FW, and sends the READY event.
- Bug fixes in the new asic PLL initialization.
- Added logic to handle CPE/RME queue interrupts before iocfc config done.
1. Use the queue_process flag to see if iocfc configuration is done
in INTX mode.
2. Split the MSIX handler installation in two - one for IOC intr
handler and the other for cpe/rme queue handler - and delay
assigning queue handlers until iocfc config is done in MSIX mode.
Signed-off-by: Krishna Gudipati <kgudipat@brocade.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
155 lines
3.4 KiB
C
155 lines
3.4 KiB
C
/*
|
|
* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
|
|
* All rights reserved
|
|
* www.brocade.com
|
|
*
|
|
* Linux driver for Brocade Fibre Channel Host Bus Adapter.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License (GPL) Version 2 as
|
|
* published by the Free Software Foundation
|
|
*
|
|
* This program is distributed in the hope that it will be useful, but
|
|
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* General Public License for more details.
|
|
*/
|
|
|
|
#include "bfad_drv.h"
|
|
#include "bfa_modules.h"
|
|
#include "bfi_reg.h"
|
|
|
|
BFA_TRC_FILE(HAL, IOCFC_CT);
|
|
|
|
/*
|
|
* Dummy interrupt handler for handling spurious interrupt during chip-reinit.
|
|
*/
|
|
static void
|
|
bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
|
|
{
|
|
}
|
|
|
|
void
|
|
bfa_hwct_reginit(struct bfa_s *bfa)
|
|
{
|
|
struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
|
|
void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
|
|
int fn = bfa_ioc_pcifn(&bfa->ioc);
|
|
|
|
if (fn == 0) {
|
|
bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
|
|
bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
|
|
} else {
|
|
bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
|
|
bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
|
|
}
|
|
}
|
|
|
|
void
|
|
bfa_hwct2_reginit(struct bfa_s *bfa)
|
|
{
|
|
struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
|
|
void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
|
|
|
|
bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS);
|
|
bfa_regs->intr_mask = (kva + CT2_HOSTFN_INTR_MASK);
|
|
}
|
|
|
|
void
|
|
bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
|
|
{
|
|
u32 r32;
|
|
|
|
r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
|
|
writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
|
|
}
|
|
|
|
void
|
|
bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq)
|
|
{
|
|
u32 r32;
|
|
|
|
r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
|
|
writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
|
|
}
|
|
|
|
void
|
|
bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
|
|
u32 *num_vecs, u32 *max_vec_bit)
|
|
{
|
|
*msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1;
|
|
*max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1));
|
|
*num_vecs = BFI_MSIX_CT_MAX;
|
|
}
|
|
|
|
/*
|
|
* Setup MSI-X vector for catapult
|
|
*/
|
|
void
|
|
bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
|
|
{
|
|
WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX));
|
|
bfa_trc(bfa, nvecs);
|
|
|
|
bfa->msix.nvecs = nvecs;
|
|
bfa_hwct_msix_uninstall(bfa);
|
|
}
|
|
|
|
void
|
|
bfa_hwct_msix_ctrl_install(struct bfa_s *bfa)
|
|
{
|
|
if (bfa->msix.nvecs == 0)
|
|
return;
|
|
|
|
if (bfa->msix.nvecs == 1)
|
|
bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_all;
|
|
else
|
|
bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err;
|
|
}
|
|
|
|
void
|
|
bfa_hwct_msix_queue_install(struct bfa_s *bfa)
|
|
{
|
|
int i;
|
|
|
|
if (bfa->msix.nvecs == 0)
|
|
return;
|
|
|
|
if (bfa->msix.nvecs == 1) {
|
|
for (i = BFI_MSIX_CPE_QMIN_CT; i < BFI_MSIX_CT_MAX; i++)
|
|
bfa->msix.handler[i] = bfa_msix_all;
|
|
return;
|
|
}
|
|
|
|
for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++)
|
|
bfa->msix.handler[i] = bfa_msix_reqq;
|
|
|
|
for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++)
|
|
bfa->msix.handler[i] = bfa_msix_rspq;
|
|
}
|
|
|
|
void
|
|
bfa_hwct_msix_uninstall(struct bfa_s *bfa)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < BFI_MSIX_CT_MAX; i++)
|
|
bfa->msix.handler[i] = bfa_hwct_msix_dummy;
|
|
}
|
|
|
|
/*
|
|
* Enable MSI-X vectors
|
|
*/
|
|
void
|
|
bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
|
|
{
|
|
bfa_trc(bfa, 0);
|
|
bfa_ioc_isr_mode_set(&bfa->ioc, msix);
|
|
}
|
|
|
|
void
|
|
bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
|
|
{
|
|
*start = BFI_MSIX_RME_QMIN_CT;
|
|
*end = BFI_MSIX_RME_QMAX_CT;
|
|
}
|