5a6704454a
BCM6338 and BCM6348 have a message control register width of 8 bits, instead of 16-bits like what the SPI driver assumes right now. Also the SPI message type shift value of 14 is actually 6 for these SoCs. This resulted in transmit FIFO corruption because we were writing 16-bits to an 8-bits wide register, thus spanning on the first byte of the transmit FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo(). Fix this by passing the message control register width and message type shift through platform data back to the SPI driver so that it can use it properly. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: grant.likely@secretlab.ca Cc: spi-devel-general@lists.sourceforge.net Cc: jonas.gorski@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/3983/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
91 lines
2.2 KiB
C
91 lines
2.2 KiB
C
#ifndef BCM63XX_DEV_SPI_H
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#define BCM63XX_DEV_SPI_H
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#include <linux/types.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_regs.h>
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int __init bcm63xx_spi_register(void);
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struct bcm63xx_spi_pdata {
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unsigned int fifo_size;
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unsigned int msg_type_shift;
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unsigned int msg_ctl_width;
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int bus_num;
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int num_chipselect;
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u32 speed_hz;
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};
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enum bcm63xx_regs_spi {
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SPI_CMD,
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SPI_INT_STATUS,
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SPI_INT_MASK_ST,
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SPI_INT_MASK,
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SPI_ST,
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SPI_CLK_CFG,
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SPI_FILL_BYTE,
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SPI_MSG_TAIL,
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SPI_RX_TAIL,
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SPI_MSG_CTL,
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SPI_MSG_DATA,
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SPI_RX_DATA,
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};
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#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
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case SPI_## __rset: \
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return SPI_## __cpu ##_## __rset;
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#define __GEN_SPI_RSET(__cpu) \
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switch (reg) { \
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__GEN_SPI_RSET_BASE(__cpu, CMD) \
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__GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
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__GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
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__GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
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__GEN_SPI_RSET_BASE(__cpu, ST) \
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__GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
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__GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
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__GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
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__GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
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__GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
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__GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
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__GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
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}
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#define __GEN_SPI_REGS_TABLE(__cpu) \
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[SPI_CMD] = SPI_## __cpu ##_CMD, \
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[SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \
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[SPI_INT_MASK_ST] = SPI_## __cpu ##_INT_MASK_ST, \
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[SPI_INT_MASK] = SPI_## __cpu ##_INT_MASK, \
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[SPI_ST] = SPI_## __cpu ##_ST, \
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[SPI_CLK_CFG] = SPI_## __cpu ##_CLK_CFG, \
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[SPI_FILL_BYTE] = SPI_## __cpu ##_FILL_BYTE, \
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[SPI_MSG_TAIL] = SPI_## __cpu ##_MSG_TAIL, \
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[SPI_RX_TAIL] = SPI_## __cpu ##_RX_TAIL, \
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[SPI_MSG_CTL] = SPI_## __cpu ##_MSG_CTL, \
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[SPI_MSG_DATA] = SPI_## __cpu ##_MSG_DATA, \
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[SPI_RX_DATA] = SPI_## __cpu ##_RX_DATA,
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static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
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{
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#ifdef BCMCPU_RUNTIME_DETECT
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extern const unsigned long *bcm63xx_regs_spi;
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return bcm63xx_regs_spi[reg];
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#else
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#ifdef CONFIG_BCM63XX_CPU_6338
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__GEN_SPI_RSET(6338)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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__GEN_SPI_RSET(6348)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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__GEN_SPI_RSET(6358)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6368
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__GEN_SPI_RSET(6368)
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#endif
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#endif
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return 0;
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}
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#endif /* BCM63XX_DEV_SPI_H */
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