8deab1144b
This is an update to the earlier patch for the sibyte headers, and superceeds the previous patch. Changes were necessary to get the tbprof driver working on the bcm1480. Patch to update Sibyte header files to match master versions maintained at Broadcom. This patch also corrects some whitespace problems, and (hopefully) shouldn't introduce any new ones. Signed-off-by: Mark Mason <mason@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
312 lines
18 KiB
C
312 lines
18 KiB
C
/* *********************************************************************
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* BCM1280/BCM1480 Board Support Package
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*
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* Interrupt Mapper definitions File: bcm1480_int.h
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*
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* This module contains constants for manipulating the
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* BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and
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* definitions for the interrupt sources.
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*
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* BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
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*
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*********************************************************************
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*
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* Copyright 2000,2001,2002,2003
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* Broadcom Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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********************************************************************* */
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#ifndef _BCM1480_INT_H
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#define _BCM1480_INT_H
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#include "sb1250_defs.h"
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/* *********************************************************************
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* Interrupt Mapper Constants
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********************************************************************* */
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/*
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* The interrupt mapper deals with 128-bit logical registers that are
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* implemented as pairs of 64-bit registers, with the "low" 64 bits in
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* a register that has an address 0x1000 higher(!) than the
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* corresponding "high" register.
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*
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* For appropriate registers, bit 0 of the "high" register is a
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* cascade bit that summarizes (as a bit-OR) the 64 bits of the "low"
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* register.
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*/
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/*
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* This entire file uses _BCM1480_ in all the symbols because it is
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* entirely BCM1480 specific.
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*/
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/*
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* Interrupt sources (Table 22)
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*/
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#define K_BCM1480_INT_SOURCES 128
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#define _BCM1480_INT_HIGH(k) (k)
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#define _BCM1480_INT_LOW(k) ((k)+64)
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#define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1)
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#define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4)
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#define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5)
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#define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6)
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#define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7)
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#define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8)
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#define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9)
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#define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10)
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#define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11)
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#define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12)
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#define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13)
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#define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14)
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#define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15)
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#define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20)
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#define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21)
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#define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22)
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#define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23)
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#define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28)
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#define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29)
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#define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30)
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#define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31)
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#define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36)
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#define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37)
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#define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38)
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#define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39)
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#define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40)
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#define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41)
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#define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42)
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#define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43)
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#define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52)
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#define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53)
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#define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54)
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#define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55)
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#define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56)
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#define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57)
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#define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58)
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#define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59)
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#define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60)
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#define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61)
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#define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62)
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#define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63)
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#define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1)
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#define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2)
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#define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3)
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#define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4)
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#define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5)
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#define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6)
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#define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7)
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#define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8)
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#define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9)
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#define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10)
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#define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11)
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#define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16)
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#define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17)
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#define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18)
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#define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19)
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#define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20)
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#define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21)
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#define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22)
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#define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23)
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#define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24)
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#define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25)
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#define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32)
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#define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33)
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#define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34)
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#define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35)
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#define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36)
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#define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40)
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#define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41)
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#define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42)
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#define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44)
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#define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45)
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#define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46)
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#define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47)
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#define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52)
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#define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53)
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#define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54)
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#define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55)
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#define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56)
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#define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57)
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#define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58)
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#define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59)
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#define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60)
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#define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61)
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#define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62)
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#define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63)
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/*
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* Mask values for each interrupt
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*/
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#define _BCM1480_INT_MASK(w,n) _SB_MAKEMASK(w,((n) & 0x3F))
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#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
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#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6)
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#define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
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#define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
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#define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
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#define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
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#define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
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#define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
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#define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
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#define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
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#define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
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#define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
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#define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
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#define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
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#define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
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#define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
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#define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
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#define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
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#define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
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#define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
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#define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
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#define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
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#define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
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#define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
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#define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
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#define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
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#define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
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#define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
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#define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
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#define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
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#define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
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#define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
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#define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
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#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
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#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
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#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
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#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8,K_BCM1480_INT_MBOX_0_0)
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#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
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#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
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#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
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#define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
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#define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
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#define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
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#define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
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#define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
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#define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
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#define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
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#define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
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#define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
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#define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
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#define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
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#define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
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#define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
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#define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
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#define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
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#define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
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#define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
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#define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
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#define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
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#define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
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#define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
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#define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
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#define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
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#define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
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#define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
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#define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
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#define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
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#define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
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#define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
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#define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
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#define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
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#define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
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#define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
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#define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
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#define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
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#define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
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#define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
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#define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
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#define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
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#define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
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#define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
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#define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
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#define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
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#define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
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#define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
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#define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
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#define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
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#define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
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#define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
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#define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
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/*
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* Interrupt mappings (Table 18)
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*/
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#define K_BCM1480_INT_MAP_I0 0 /* interrupt pins on processor */
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#define K_BCM1480_INT_MAP_I1 1
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#define K_BCM1480_INT_MAP_I2 2
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#define K_BCM1480_INT_MAP_I3 3
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#define K_BCM1480_INT_MAP_I4 4
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#define K_BCM1480_INT_MAP_I5 5
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#define K_BCM1480_INT_MAP_NMI 6 /* nonmaskable */
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#define K_BCM1480_INT_MAP_DINT 7 /* debug interrupt */
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/*
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* Interrupt LDT Set Register (Table 19)
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*/
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#define S_BCM1480_INT_HT_INTMSG 0
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#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG)
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#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG)
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#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG)
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#define K_BCM1480_INT_HT_INTMSG_FIXED 0
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#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1
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#define K_BCM1480_INT_HT_INTMSG_SMI 2
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#define K_BCM1480_INT_HT_INTMSG_NMI 3
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#define K_BCM1480_INT_HT_INTMSG_INIT 4
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#define K_BCM1480_INT_HT_INTMSG_STARTUP 5
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#define K_BCM1480_INT_HT_INTMSG_EXTINT 6
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#define K_BCM1480_INT_HT_INTMSG_RESERVED 7
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#define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3)
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#define V_BCM1480_INT_HT_EDGETRIGGER 0
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#define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE
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#define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4)
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#define V_BCM1480_INT_HT_PHYSICALDEST 0
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#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE
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#define S_BCM1480_INT_HT_INTDEST 5
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#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST)
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#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST)
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#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST)
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#define S_BCM1480_INT_HT_VECTOR 13
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#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR)
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#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR)
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#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR)
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/*
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* Vector prefix (Table 4-7)
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*/
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#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00
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#define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40
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#define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80
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#define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0
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#endif /* _BCM1480_INT_H */
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