2b5987abaf
We reserve the 3.75GB - 4GB region of PCIe address space for device to device transfers, making the corresponding physical memory under direct mapping unavailable for DMA. To allow for PCIe DMA to all physical memory we map this chunk of physical memory with BAR1. Because of the resulting discontinuity in the mapping function, we remove a page of memory at each end of the range so multi-page DMA buffers can never be allocated that span the range. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1535/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
342 lines
10 KiB
C
342 lines
10 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
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* Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org>
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* Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
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* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
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* IP32 changes by Ilya.
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* Cavium Networks: Create new dma setup for Cavium Networks Octeon based on
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* the kernels original.
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/cache.h>
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#include <linux/io.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-npi-defs.h>
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#include <asm/octeon/cvmx-pci-defs.h>
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#include <dma-coherence.h>
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#ifdef CONFIG_PCI
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#include <asm/octeon/pci-octeon.h>
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#endif
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#define BAR2_PCI_ADDRESS 0x8000000000ul
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struct bar1_index_state {
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int16_t ref_count; /* Number of PCI mappings using this index */
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uint16_t address_bits; /* Upper bits of physical address. This is
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shifted 22 bits */
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};
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#ifdef CONFIG_PCI
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static DEFINE_RAW_SPINLOCK(bar1_lock);
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static struct bar1_index_state bar1_state[32];
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#endif
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dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
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{
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#ifndef CONFIG_PCI
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/* Without PCI/PCIe this function can be called for Octeon internal
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devices such as USB. These devices all support 64bit addressing */
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mb();
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return virt_to_phys(ptr);
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#else
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unsigned long flags;
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uint64_t dma_mask;
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int64_t start_index;
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dma_addr_t result = -1;
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uint64_t physical = virt_to_phys(ptr);
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int64_t index;
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mb();
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/*
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* Use the DMA masks to determine the allowed memory
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* region. For us it doesn't limit the actual memory, just the
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* address visible over PCI. Devices with limits need to use
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* lower indexed Bar1 entries.
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*/
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if (dev) {
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dma_mask = dev->coherent_dma_mask;
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if (dev->dma_mask)
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dma_mask = *dev->dma_mask;
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} else {
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dma_mask = 0xfffffffful;
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}
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/*
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* Platform devices, such as the internal USB, skip all
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* translation and use Octeon physical addresses directly.
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*/
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if (!dev || dev->bus == &platform_bus_type)
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return physical;
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switch (octeon_dma_bar_type) {
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case OCTEON_DMA_BAR_TYPE_PCIE:
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if (unlikely(physical < (16ul << 10)))
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panic("dma_map_single: Not allowed to map first 16KB."
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" It interferes with BAR0 special area\n");
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else if ((physical + size >= (256ul << 20)) &&
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(physical < (512ul << 20)))
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panic("dma_map_single: Not allowed to map bootbus\n");
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else if ((physical + size >= 0x400000000ull) &&
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physical < 0x410000000ull)
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panic("dma_map_single: "
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"Attempt to map illegal memory address 0x%llx\n",
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physical);
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else if (physical >= 0x420000000ull)
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panic("dma_map_single: "
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"Attempt to map illegal memory address 0x%llx\n",
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physical);
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else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
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physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
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result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
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if (((result+size-1) & dma_mask) != result+size-1)
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panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
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physical, physical+size-1, dma_mask);
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goto done;
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}
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/* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
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if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
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result = physical - 0x400000000ull;
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else
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result = physical;
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if (((result+size-1) & dma_mask) != result+size-1)
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panic("dma_map_single: Attempt to map address "
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"0x%llx-0x%llx, which can't be accessed "
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"according to the dma mask 0x%llx\n",
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physical, physical+size-1, dma_mask);
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goto done;
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case OCTEON_DMA_BAR_TYPE_BIG:
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#ifdef CONFIG_64BIT
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/* If the device supports 64bit addressing, then use BAR2 */
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if (dma_mask > BAR2_PCI_ADDRESS) {
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result = physical + BAR2_PCI_ADDRESS;
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goto done;
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}
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#endif
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if (unlikely(physical < (4ul << 10))) {
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panic("dma_map_single: Not allowed to map first 4KB. "
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"It interferes with BAR0 special area\n");
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} else if (physical < (256ul << 20)) {
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if (unlikely(physical + size > (256ul << 20)))
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panic("dma_map_single: Requested memory spans "
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"Bar0 0:256MB and bootbus\n");
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result = physical;
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goto done;
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} else if (unlikely(physical < (512ul << 20))) {
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panic("dma_map_single: Not allowed to map bootbus\n");
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} else if (physical < (2ul << 30)) {
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if (unlikely(physical + size > (2ul << 30)))
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panic("dma_map_single: Requested memory spans "
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"Bar0 512MB:2GB and BAR1\n");
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result = physical;
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goto done;
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} else if (physical < (2ul << 30) + (128 << 20)) {
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/* Fall through */
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} else if (physical <
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(4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
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if (unlikely
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(physical + size >
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(4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
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panic("dma_map_single: Requested memory "
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"extends past Bar1 (4GB-%luMB)\n",
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OCTEON_PCI_BAR1_HOLE_SIZE);
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result = physical;
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goto done;
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} else if ((physical >= 0x410000000ull) &&
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(physical < 0x420000000ull)) {
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if (unlikely(physical + size > 0x420000000ull))
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panic("dma_map_single: Requested memory spans "
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"non existant memory\n");
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/* BAR0 fixed mapping 256MB:512MB ->
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* 16GB+256MB:16GB+512MB */
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result = physical - 0x400000000ull;
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goto done;
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} else {
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/* Continued below switch statement */
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}
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break;
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case OCTEON_DMA_BAR_TYPE_SMALL:
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#ifdef CONFIG_64BIT
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/* If the device supports 64bit addressing, then use BAR2 */
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if (dma_mask > BAR2_PCI_ADDRESS) {
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result = physical + BAR2_PCI_ADDRESS;
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goto done;
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}
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#endif
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/* Continued below switch statement */
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break;
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default:
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panic("dma_map_single: Invalid octeon_dma_bar_type\n");
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}
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/* Don't allow mapping to span multiple Bar entries. The hardware guys
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won't guarantee that DMA across boards work */
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if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
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panic("dma_map_single: "
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"Requested memory spans more than one Bar1 entry\n");
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if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
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start_index = 31;
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else if (unlikely(dma_mask < (1ul << 27)))
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start_index = (dma_mask >> 22);
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else
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start_index = 31;
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/* Only one processor can access the Bar register at once */
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raw_spin_lock_irqsave(&bar1_lock, flags);
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/* Look through Bar1 for existing mapping that will work */
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for (index = start_index; index >= 0; index--) {
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if ((bar1_state[index].address_bits == physical >> 22) &&
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(bar1_state[index].ref_count)) {
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/* An existing mapping will work, use it */
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bar1_state[index].ref_count++;
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if (unlikely(bar1_state[index].ref_count < 0))
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panic("dma_map_single: "
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"Bar1[%d] reference count overflowed\n",
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(int) index);
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result = (index << 22) | (physical & ((1 << 22) - 1));
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/* Large BAR1 is offset at 2GB */
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if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
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result += 2ul << 30;
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goto done_unlock;
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}
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}
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/* No existing mappings, look for a free entry */
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for (index = start_index; index >= 0; index--) {
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if (unlikely(bar1_state[index].ref_count == 0)) {
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union cvmx_pci_bar1_indexx bar1_index;
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/* We have a free entry, use it */
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bar1_state[index].ref_count = 1;
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bar1_state[index].address_bits = physical >> 22;
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bar1_index.u32 = 0;
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/* Address bits[35:22] sent to L2C */
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bar1_index.s.addr_idx = physical >> 22;
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/* Don't put PCI accesses in L2. */
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bar1_index.s.ca = 1;
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/* Endian Swap Mode */
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bar1_index.s.end_swp = 1;
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/* Set '1' when the selected address range is valid. */
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bar1_index.s.addr_v = 1;
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octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
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bar1_index.u32);
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/* An existing mapping will work, use it */
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result = (index << 22) | (physical & ((1 << 22) - 1));
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/* Large BAR1 is offset at 2GB */
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if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
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result += 2ul << 30;
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goto done_unlock;
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}
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}
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pr_err("dma_map_single: "
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"Can't find empty BAR1 index for physical mapping 0x%llx\n",
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(unsigned long long) physical);
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done_unlock:
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raw_spin_unlock_irqrestore(&bar1_lock, flags);
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done:
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pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result);
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return result;
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#endif
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}
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void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
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{
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#ifndef CONFIG_PCI
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/*
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* Without PCI/PCIe this function can be called for Octeon internal
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* devices such as USB. These devices all support 64bit addressing.
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*/
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return;
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#else
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unsigned long flags;
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uint64_t index;
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/*
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* Platform devices, such as the internal USB, skip all
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* translation and use Octeon physical addresses directly.
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*/
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if (dev->bus == &platform_bus_type)
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return;
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switch (octeon_dma_bar_type) {
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case OCTEON_DMA_BAR_TYPE_PCIE:
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/* Nothing to do, all mappings are static */
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goto done;
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case OCTEON_DMA_BAR_TYPE_BIG:
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#ifdef CONFIG_64BIT
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/* Nothing to do for addresses using BAR2 */
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if (dma_addr >= BAR2_PCI_ADDRESS)
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goto done;
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#endif
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if (unlikely(dma_addr < (4ul << 10)))
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panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
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dma_addr);
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else if (dma_addr < (2ul << 30))
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/* Nothing to do for addresses using BAR0 */
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goto done;
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else if (dma_addr < (2ul << 30) + (128ul << 20))
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/* Need to unmap, fall through */
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index = (dma_addr - (2ul << 30)) >> 22;
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else if (dma_addr <
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(4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
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goto done; /* Nothing to do for the rest of BAR1 */
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else
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panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
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dma_addr);
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/* Continued below switch statement */
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break;
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case OCTEON_DMA_BAR_TYPE_SMALL:
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#ifdef CONFIG_64BIT
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/* Nothing to do for addresses using BAR2 */
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if (dma_addr >= BAR2_PCI_ADDRESS)
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goto done;
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#endif
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index = dma_addr >> 22;
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/* Continued below switch statement */
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break;
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default:
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panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
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}
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if (unlikely(index > 31))
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panic("dma_unmap_single: "
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"Attempt to unmap an invalid address (0x%llx)\n",
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dma_addr);
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raw_spin_lock_irqsave(&bar1_lock, flags);
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bar1_state[index].ref_count--;
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if (bar1_state[index].ref_count == 0)
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octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
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else if (unlikely(bar1_state[index].ref_count < 0))
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panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
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(int) index);
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raw_spin_unlock_irqrestore(&bar1_lock, flags);
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done:
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pr_debug("dma_unmap_single 0x%llx\n", dma_addr);
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return;
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#endif
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}
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