c53c9cf60e
Add core support for the Kendin/Micrel KS8695 processor family. It is an ARM922-T based SoC with integrated USART, 4-port Ethernet Switch, WAN Ethernet port, and optional PCI Host bridge, etc. http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp This patch is based on earlier patches from Lennert Buytenhek, Ben Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in March 2006; and Micrel's 2.6.9 port. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
97 lines
3.5 KiB
C
97 lines
3.5 KiB
C
/*
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* include/asm-arm/arch-ks8695/regs-misc.h
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*
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* Copyright (C) 2006 Andrew Victor
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*
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* KS8695 - Miscellaneous Registers
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef KS8695_MISC_H
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#define KS8695_MISC_H
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#define KS8695_MISC_OFFSET (0xF0000 + 0xEA00)
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#define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET)
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#define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET)
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/*
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* Miscellaneous registers
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*/
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#define KS8695_DID (0x00) /* Device ID */
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#define KS8695_RID (0x04) /* Revision ID */
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#define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */
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#define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */
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#define KS8695_WPPM (0x10) /* WAN PHY Power Management */
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#define KS8695_PPS (0x1c) /* PHY PowerSave */
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/* Device ID Register */
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#define DID_ID (0xffff << 0) /* Device ID */
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/* Revision ID Register */
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#define RID_SUBID (0xf << 4) /* Sub-Device ID */
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#define RID_REVISION (0xf << 0) /* Revision ID */
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/* HPNA Miscellaneous Control Register */
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#define HMC_HSS (1 << 1) /* Speed */
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#define HMC_HDS (1 << 0) /* Duplex */
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/* WAN Miscellaneous Control Register */
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#define WMC_WANC (1 << 30) /* Auto-negotiation complete */
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#define WMC_WANR (1 << 29) /* Auto-negotiation restart */
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#define WMC_WANAP (1 << 28) /* Advertise Pause */
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#define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */
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#define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */
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#define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */
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#define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */
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#define WMC_WLS (1 << 23) /* Link status */
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#define WMC_WDS (1 << 22) /* Duplex status */
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#define WMC_WSS (1 << 21) /* Speed status */
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#define WMC_WLPP (1 << 20) /* Link Partner Pause */
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#define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */
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#define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */
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#define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */
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#define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */
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#define WMC_WAND (1 << 15) /* Auto-negotiation disable */
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#define WMC_WANF100 (1 << 14) /* Force 100 */
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#define WMC_WANFF (1 << 13) /* Force FDX */
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#define WMC_WLED1S (7 << 4) /* LED1 Select */
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#define WLED1S_SPEED (0 << 4)
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#define WLED1S_LINK (1 << 4)
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#define WLED1S_DUPLEX (2 << 4)
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#define WLED1S_COLLISION (3 << 4)
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#define WLED1S_ACTIVITY (4 << 4)
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#define WLED1S_FDX_COLLISION (5 << 4)
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#define WLED1S_LINK_ACTIVITY (6 << 4)
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#define WMC_WLED0S (7 << 0) /* LED0 Select */
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#define WLED0S_SPEED (0 << 0)
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#define WLED0S_LINK (1 << 0)
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#define WLED0S_DUPLEX (2 << 0)
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#define WLED0S_COLLISION (3 << 0)
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#define WLED0S_ACTIVITY (4 << 0)
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#define WLED0S_FDX_COLLISION (5 << 0)
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#define WLED0S_LINK_ACTIVITY (6 << 0)
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/* WAN PHY Power Management Register */
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#define WPPM_WLPBK (1 << 14) /* Local Loopback */
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#define WPPM_WRLPKB (1 << 13) /* Remove Loopback */
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#define WPPM_WPI (1 << 12) /* PHY isolate */
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#define WPPM_WFL (1 << 10) /* Force link */
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#define WPPM_MDIXS (1 << 9) /* MDIX Status */
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#define WPPM_FEF (1 << 8) /* Far End Fault */
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#define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */
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#define WPPM_TXDIS (1 << 6) /* Disable transmitter */
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#define WPPM_DFEF (1 << 5) /* Disable Far End Fault */
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#define WPPM_PD (1 << 4) /* Power Down */
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#define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */
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#define WPPM_FMDX (1 << 2) /* Force MDIX */
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#define WPPM_LPBK (1 << 1) /* MAX Loopback */
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/* PHY Power Save Register */
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#define PPS_PPSM (1 << 0) /* PHY Power Save Mode */
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#endif
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