1257 lines
31 KiB
C
1257 lines
31 KiB
C
/*
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* drivers/mtd/nand/pxa3xx_nand.c
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*
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* Copyright © 2005 Intel Corporation
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* Copyright © 2006 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <mach/dma.h>
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#include <plat/pxa3xx_nand.h>
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#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
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#define NAND_STOP_DELAY (2 * HZ/50)
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#define PAGE_CHUNK_SIZE (2048)
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/* registers and bit definitions */
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#define NDCR (0x00) /* Control register */
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#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
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#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
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#define NDSR (0x14) /* Status Register */
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#define NDPCR (0x18) /* Page Count Register */
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#define NDBDR0 (0x1C) /* Bad Block Register 0 */
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#define NDBDR1 (0x20) /* Bad Block Register 1 */
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#define NDDB (0x40) /* Data Buffer */
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#define NDCB0 (0x48) /* Command Buffer0 */
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#define NDCB1 (0x4C) /* Command Buffer1 */
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#define NDCB2 (0x50) /* Command Buffer2 */
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#define NDCR_SPARE_EN (0x1 << 31)
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#define NDCR_ECC_EN (0x1 << 30)
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#define NDCR_DMA_EN (0x1 << 29)
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#define NDCR_ND_RUN (0x1 << 28)
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#define NDCR_DWIDTH_C (0x1 << 27)
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#define NDCR_DWIDTH_M (0x1 << 26)
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#define NDCR_PAGE_SZ (0x1 << 24)
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#define NDCR_NCSX (0x1 << 23)
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#define NDCR_ND_MODE (0x3 << 21)
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#define NDCR_NAND_MODE (0x0)
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#define NDCR_CLR_PG_CNT (0x1 << 20)
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#define NDCR_STOP_ON_UNCOR (0x1 << 19)
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#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
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#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
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#define NDCR_RA_START (0x1 << 15)
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#define NDCR_PG_PER_BLK (0x1 << 14)
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#define NDCR_ND_ARB_EN (0x1 << 12)
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#define NDCR_INT_MASK (0xFFF)
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#define NDSR_MASK (0xfff)
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#define NDSR_RDY (0x1 << 12)
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#define NDSR_FLASH_RDY (0x1 << 11)
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#define NDSR_CS0_PAGED (0x1 << 10)
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#define NDSR_CS1_PAGED (0x1 << 9)
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#define NDSR_CS0_CMDD (0x1 << 8)
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#define NDSR_CS1_CMDD (0x1 << 7)
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#define NDSR_CS0_BBD (0x1 << 6)
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#define NDSR_CS1_BBD (0x1 << 5)
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#define NDSR_DBERR (0x1 << 4)
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#define NDSR_SBERR (0x1 << 3)
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#define NDSR_WRDREQ (0x1 << 2)
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#define NDSR_RDDREQ (0x1 << 1)
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#define NDSR_WRCMDREQ (0x1)
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#define NDCB0_ST_ROW_EN (0x1 << 26)
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#define NDCB0_AUTO_RS (0x1 << 25)
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#define NDCB0_CSEL (0x1 << 24)
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#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
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#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
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#define NDCB0_NC (0x1 << 20)
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#define NDCB0_DBC (0x1 << 19)
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#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
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#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
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#define NDCB0_CMD2_MASK (0xff << 8)
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#define NDCB0_CMD1_MASK (0xff)
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#define NDCB0_ADDR_CYC_SHIFT (16)
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/* macros for registers read/write */
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#define nand_writel(info, off, val) \
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__raw_writel((val), (info)->mmio_base + (off))
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#define nand_readl(info, off) \
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__raw_readl((info)->mmio_base + (off))
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/* error code and state */
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enum {
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ERR_NONE = 0,
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ERR_DMABUSERR = -1,
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ERR_SENDCMD = -2,
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ERR_DBERR = -3,
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ERR_BBERR = -4,
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ERR_SBERR = -5,
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};
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enum {
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STATE_IDLE = 0,
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STATE_CMD_HANDLE,
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STATE_DMA_READING,
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STATE_DMA_WRITING,
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STATE_DMA_DONE,
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STATE_PIO_READING,
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STATE_PIO_WRITING,
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STATE_CMD_DONE,
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STATE_READY,
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};
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struct pxa3xx_nand_info {
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struct nand_chip nand_chip;
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struct nand_hw_control controller;
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struct platform_device *pdev;
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struct pxa3xx_nand_cmdset *cmdset;
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struct clk *clk;
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void __iomem *mmio_base;
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unsigned long mmio_phys;
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unsigned int buf_start;
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unsigned int buf_count;
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struct mtd_info *mtd;
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/* DMA information */
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int drcmr_dat;
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int drcmr_cmd;
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unsigned char *data_buff;
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unsigned char *oob_buff;
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dma_addr_t data_buff_phys;
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size_t data_buff_size;
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int data_dma_ch;
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struct pxa_dma_desc *data_desc;
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dma_addr_t data_desc_addr;
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uint32_t reg_ndcr;
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/* saved column/page_addr during CMD_SEQIN */
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int seqin_column;
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int seqin_page_addr;
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/* relate to the command */
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unsigned int state;
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int use_ecc; /* use HW ECC ? */
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int use_dma; /* use DMA ? */
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int is_ready;
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unsigned int page_size; /* page size of attached chip */
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unsigned int data_size; /* data size in FIFO */
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int retcode;
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struct completion cmd_complete;
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/* generated NDCBx register values */
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uint32_t ndcb0;
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uint32_t ndcb1;
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uint32_t ndcb2;
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/* timing calcuted from setting */
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uint32_t ndtr0cs0;
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uint32_t ndtr1cs0;
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/* calculated from pxa3xx_nand_flash data */
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size_t oob_size;
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size_t read_id_bytes;
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unsigned int col_addr_cycles;
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unsigned int row_addr_cycles;
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};
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static int use_dma = 1;
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module_param(use_dma, bool, 0444);
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MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
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/*
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* Default NAND flash controller configuration setup by the
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* bootloader. This configuration is used only when pdata->keep_config is set
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*/
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static struct pxa3xx_nand_cmdset default_cmdset = {
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.read1 = 0x3000,
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.read2 = 0x0050,
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.program = 0x1080,
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.read_status = 0x0070,
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.read_id = 0x0090,
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.erase = 0xD060,
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.reset = 0x00FF,
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.lock = 0x002A,
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.unlock = 0x2423,
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.lock_status = 0x007A,
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};
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static struct pxa3xx_nand_timing timing[] = {
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{ 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
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{ 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
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{ 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
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{ 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
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};
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static struct pxa3xx_nand_flash builtin_flash_types[] = {
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{ 0, 0, 2048, 8, 8, 0, &default_cmdset, &timing[0] },
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{ 0x46ec, 32, 512, 16, 16, 4096, &default_cmdset, &timing[1] },
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{ 0xdaec, 64, 2048, 8, 8, 2048, &default_cmdset, &timing[1] },
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{ 0xd7ec, 128, 4096, 8, 8, 8192, &default_cmdset, &timing[1] },
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{ 0xa12c, 64, 2048, 8, 8, 1024, &default_cmdset, &timing[2] },
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{ 0xb12c, 64, 2048, 16, 16, 1024, &default_cmdset, &timing[2] },
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{ 0xdc2c, 64, 2048, 8, 8, 4096, &default_cmdset, &timing[2] },
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{ 0xcc2c, 64, 2048, 16, 16, 4096, &default_cmdset, &timing[2] },
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{ 0xba20, 64, 2048, 16, 16, 2048, &default_cmdset, &timing[3] },
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};
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/* Define a default flash type setting serve as flash detecting only */
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#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
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const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
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#define NDTR0_tCH(c) (min((c), 7) << 19)
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#define NDTR0_tCS(c) (min((c), 7) << 16)
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#define NDTR0_tWH(c) (min((c), 7) << 11)
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#define NDTR0_tWP(c) (min((c), 7) << 8)
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#define NDTR0_tRH(c) (min((c), 7) << 3)
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#define NDTR0_tRP(c) (min((c), 7) << 0)
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#define NDTR1_tR(c) (min((c), 65535) << 16)
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#define NDTR1_tWHR(c) (min((c), 15) << 4)
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#define NDTR1_tAR(c) (min((c), 15) << 0)
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/* convert nano-seconds to nand flash controller clock cycles */
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#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
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static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
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const struct pxa3xx_nand_timing *t)
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{
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unsigned long nand_clk = clk_get_rate(info->clk);
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uint32_t ndtr0, ndtr1;
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ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
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NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
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NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
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NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
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NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
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NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
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ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
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NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
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NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
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info->ndtr0cs0 = ndtr0;
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info->ndtr1cs0 = ndtr1;
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nand_writel(info, NDTR0CS0, ndtr0);
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nand_writel(info, NDTR1CS0, ndtr1);
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}
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static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
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{
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int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
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info->data_size = info->page_size;
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if (!oob_enable) {
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info->oob_size = 0;
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return;
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}
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switch (info->page_size) {
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case 2048:
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info->oob_size = (info->use_ecc) ? 40 : 64;
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break;
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case 512:
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info->oob_size = (info->use_ecc) ? 8 : 16;
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break;
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}
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}
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/**
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* NOTE: it is a must to set ND_RUN firstly, then write
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* command buffer, otherwise, it does not work.
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* We enable all the interrupt at the same time, and
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* let pxa3xx_nand_irq to handle all logic.
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*/
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static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
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{
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uint32_t ndcr;
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ndcr = info->reg_ndcr;
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ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
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ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
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ndcr |= NDCR_ND_RUN;
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/* clear status bits and run */
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nand_writel(info, NDCR, 0);
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nand_writel(info, NDSR, NDSR_MASK);
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nand_writel(info, NDCR, ndcr);
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}
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static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
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{
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uint32_t ndcr;
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int timeout = NAND_STOP_DELAY;
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/* wait RUN bit in NDCR become 0 */
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ndcr = nand_readl(info, NDCR);
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while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
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ndcr = nand_readl(info, NDCR);
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udelay(1);
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}
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if (timeout <= 0) {
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ndcr &= ~NDCR_ND_RUN;
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nand_writel(info, NDCR, ndcr);
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}
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/* clear status bits */
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nand_writel(info, NDSR, NDSR_MASK);
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}
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static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
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{
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uint32_t ndcr;
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ndcr = nand_readl(info, NDCR);
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nand_writel(info, NDCR, ndcr & ~int_mask);
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}
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static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
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{
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uint32_t ndcr;
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ndcr = nand_readl(info, NDCR);
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nand_writel(info, NDCR, ndcr | int_mask);
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}
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static void handle_data_pio(struct pxa3xx_nand_info *info)
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{
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switch (info->state) {
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case STATE_PIO_WRITING:
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__raw_writesl(info->mmio_base + NDDB, info->data_buff,
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DIV_ROUND_UP(info->data_size, 4));
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if (info->oob_size > 0)
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__raw_writesl(info->mmio_base + NDDB, info->oob_buff,
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DIV_ROUND_UP(info->oob_size, 4));
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break;
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case STATE_PIO_READING:
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__raw_readsl(info->mmio_base + NDDB, info->data_buff,
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DIV_ROUND_UP(info->data_size, 4));
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if (info->oob_size > 0)
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__raw_readsl(info->mmio_base + NDDB, info->oob_buff,
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DIV_ROUND_UP(info->oob_size, 4));
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break;
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default:
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printk(KERN_ERR "%s: invalid state %d\n", __func__,
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info->state);
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BUG();
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}
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}
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static void start_data_dma(struct pxa3xx_nand_info *info)
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{
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struct pxa_dma_desc *desc = info->data_desc;
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int dma_len = ALIGN(info->data_size + info->oob_size, 32);
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desc->ddadr = DDADR_STOP;
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desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
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switch (info->state) {
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case STATE_DMA_WRITING:
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desc->dsadr = info->data_buff_phys;
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desc->dtadr = info->mmio_phys + NDDB;
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desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
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break;
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case STATE_DMA_READING:
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desc->dtadr = info->data_buff_phys;
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desc->dsadr = info->mmio_phys + NDDB;
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desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
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break;
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default:
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printk(KERN_ERR "%s: invalid state %d\n", __func__,
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info->state);
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BUG();
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}
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DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
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DDADR(info->data_dma_ch) = info->data_desc_addr;
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DCSR(info->data_dma_ch) |= DCSR_RUN;
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}
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static void pxa3xx_nand_data_dma_irq(int channel, void *data)
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{
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struct pxa3xx_nand_info *info = data;
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uint32_t dcsr;
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dcsr = DCSR(channel);
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DCSR(channel) = dcsr;
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if (dcsr & DCSR_BUSERR) {
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info->retcode = ERR_DMABUSERR;
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}
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info->state = STATE_DMA_DONE;
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enable_int(info, NDCR_INT_MASK);
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nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
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}
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static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
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{
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struct pxa3xx_nand_info *info = devid;
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unsigned int status, is_completed = 0;
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status = nand_readl(info, NDSR);
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if (status & NDSR_DBERR)
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info->retcode = ERR_DBERR;
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if (status & NDSR_SBERR)
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info->retcode = ERR_SBERR;
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if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
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/* whether use dma to transfer data */
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if (info->use_dma) {
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disable_int(info, NDCR_INT_MASK);
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info->state = (status & NDSR_RDDREQ) ?
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STATE_DMA_READING : STATE_DMA_WRITING;
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start_data_dma(info);
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goto NORMAL_IRQ_EXIT;
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} else {
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info->state = (status & NDSR_RDDREQ) ?
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STATE_PIO_READING : STATE_PIO_WRITING;
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handle_data_pio(info);
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}
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}
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if (status & NDSR_CS0_CMDD) {
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info->state = STATE_CMD_DONE;
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is_completed = 1;
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}
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if (status & NDSR_FLASH_RDY) {
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info->is_ready = 1;
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info->state = STATE_READY;
|
|
}
|
|
|
|
if (status & NDSR_WRCMDREQ) {
|
|
nand_writel(info, NDSR, NDSR_WRCMDREQ);
|
|
status &= ~NDSR_WRCMDREQ;
|
|
info->state = STATE_CMD_HANDLE;
|
|
nand_writel(info, NDCB0, info->ndcb0);
|
|
nand_writel(info, NDCB0, info->ndcb1);
|
|
nand_writel(info, NDCB0, info->ndcb2);
|
|
}
|
|
|
|
/* clear NDSR to let the controller exit the IRQ */
|
|
nand_writel(info, NDSR, status);
|
|
if (is_completed)
|
|
complete(&info->cmd_complete);
|
|
NORMAL_IRQ_EXIT:
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
|
|
{
|
|
struct pxa3xx_nand_info *info = mtd->priv;
|
|
return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
|
|
}
|
|
|
|
static inline int is_buf_blank(uint8_t *buf, size_t len)
|
|
{
|
|
for (; len > 0; len--)
|
|
if (*buf++ != 0xff)
|
|
return 0;
|
|
return 1;
|
|
}
|
|
|
|
static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
|
|
uint16_t column, int page_addr)
|
|
{
|
|
uint16_t cmd;
|
|
int addr_cycle, exec_cmd, ndcb0;
|
|
struct mtd_info *mtd = info->mtd;
|
|
|
|
ndcb0 = 0;
|
|
addr_cycle = 0;
|
|
exec_cmd = 1;
|
|
|
|
/* reset data and oob column point to handle data */
|
|
info->buf_start = 0;
|
|
info->buf_count = 0;
|
|
info->oob_size = 0;
|
|
info->use_ecc = 0;
|
|
info->is_ready = 0;
|
|
info->retcode = ERR_NONE;
|
|
|
|
switch (command) {
|
|
case NAND_CMD_READ0:
|
|
case NAND_CMD_PAGEPROG:
|
|
info->use_ecc = 1;
|
|
case NAND_CMD_READOOB:
|
|
pxa3xx_set_datasize(info);
|
|
break;
|
|
case NAND_CMD_SEQIN:
|
|
exec_cmd = 0;
|
|
break;
|
|
default:
|
|
info->ndcb1 = 0;
|
|
info->ndcb2 = 0;
|
|
break;
|
|
}
|
|
|
|
info->ndcb0 = ndcb0;
|
|
addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
|
|
+ info->col_addr_cycles);
|
|
|
|
switch (command) {
|
|
case NAND_CMD_READOOB:
|
|
case NAND_CMD_READ0:
|
|
cmd = info->cmdset->read1;
|
|
if (command == NAND_CMD_READOOB)
|
|
info->buf_start = mtd->writesize + column;
|
|
else
|
|
info->buf_start = column;
|
|
|
|
if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
|
|
info->ndcb0 |= NDCB0_CMD_TYPE(0)
|
|
| addr_cycle
|
|
| (cmd & NDCB0_CMD1_MASK);
|
|
else
|
|
info->ndcb0 |= NDCB0_CMD_TYPE(0)
|
|
| NDCB0_DBC
|
|
| addr_cycle
|
|
| cmd;
|
|
|
|
case NAND_CMD_SEQIN:
|
|
/* small page addr setting */
|
|
if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) {
|
|
info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
|
|
| (column & 0xFF);
|
|
|
|
info->ndcb2 = 0;
|
|
} else {
|
|
info->ndcb1 = ((page_addr & 0xFFFF) << 16)
|
|
| (column & 0xFFFF);
|
|
|
|
if (page_addr & 0xFF0000)
|
|
info->ndcb2 = (page_addr & 0xFF0000) >> 16;
|
|
else
|
|
info->ndcb2 = 0;
|
|
}
|
|
|
|
info->buf_count = mtd->writesize + mtd->oobsize;
|
|
memset(info->data_buff, 0xFF, info->buf_count);
|
|
|
|
break;
|
|
|
|
case NAND_CMD_PAGEPROG:
|
|
if (is_buf_blank(info->data_buff,
|
|
(mtd->writesize + mtd->oobsize))) {
|
|
exec_cmd = 0;
|
|
break;
|
|
}
|
|
|
|
cmd = info->cmdset->program;
|
|
info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
|
|
| NDCB0_AUTO_RS
|
|
| NDCB0_ST_ROW_EN
|
|
| NDCB0_DBC
|
|
| cmd
|
|
| addr_cycle;
|
|
break;
|
|
|
|
case NAND_CMD_READID:
|
|
cmd = info->cmdset->read_id;
|
|
info->buf_count = info->read_id_bytes;
|
|
info->ndcb0 |= NDCB0_CMD_TYPE(3)
|
|
| NDCB0_ADDR_CYC(1)
|
|
| cmd;
|
|
|
|
info->data_size = 8;
|
|
break;
|
|
case NAND_CMD_STATUS:
|
|
cmd = info->cmdset->read_status;
|
|
info->buf_count = 1;
|
|
info->ndcb0 |= NDCB0_CMD_TYPE(4)
|
|
| NDCB0_ADDR_CYC(1)
|
|
| cmd;
|
|
|
|
info->data_size = 8;
|
|
break;
|
|
|
|
case NAND_CMD_ERASE1:
|
|
cmd = info->cmdset->erase;
|
|
info->ndcb0 |= NDCB0_CMD_TYPE(2)
|
|
| NDCB0_AUTO_RS
|
|
| NDCB0_ADDR_CYC(3)
|
|
| NDCB0_DBC
|
|
| cmd;
|
|
info->ndcb1 = page_addr;
|
|
info->ndcb2 = 0;
|
|
|
|
break;
|
|
case NAND_CMD_RESET:
|
|
cmd = info->cmdset->reset;
|
|
info->ndcb0 |= NDCB0_CMD_TYPE(5)
|
|
| cmd;
|
|
|
|
break;
|
|
|
|
case NAND_CMD_ERASE2:
|
|
exec_cmd = 0;
|
|
break;
|
|
|
|
default:
|
|
exec_cmd = 0;
|
|
printk(KERN_ERR "pxa3xx-nand: non-supported"
|
|
" command %x\n", command);
|
|
break;
|
|
}
|
|
|
|
return exec_cmd;
|
|
}
|
|
|
|
static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
|
|
int column, int page_addr)
|
|
{
|
|
struct pxa3xx_nand_info *info = mtd->priv;
|
|
int ret, exec_cmd;
|
|
|
|
/*
|
|
* if this is a x16 device ,then convert the input
|
|
* "byte" address into a "word" address appropriate
|
|
* for indexing a word-oriented device
|
|
*/
|
|
if (info->reg_ndcr & NDCR_DWIDTH_M)
|
|
column /= 2;
|
|
|
|
exec_cmd = prepare_command_pool(info, command, column, page_addr);
|
|
if (exec_cmd) {
|
|
init_completion(&info->cmd_complete);
|
|
pxa3xx_nand_start(info);
|
|
|
|
ret = wait_for_completion_timeout(&info->cmd_complete,
|
|
CHIP_DELAY_TIMEOUT);
|
|
if (!ret) {
|
|
printk(KERN_ERR "Wait time out!!!\n");
|
|
/* Stop State Machine for next command cycle */
|
|
pxa3xx_nand_stop(info);
|
|
}
|
|
info->state = STATE_IDLE;
|
|
}
|
|
}
|
|
|
|
static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
|
|
struct nand_chip *chip, const uint8_t *buf)
|
|
{
|
|
chip->write_buf(mtd, buf, mtd->writesize);
|
|
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
}
|
|
|
|
static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
|
|
struct nand_chip *chip, uint8_t *buf, int page)
|
|
{
|
|
struct pxa3xx_nand_info *info = mtd->priv;
|
|
|
|
chip->read_buf(mtd, buf, mtd->writesize);
|
|
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
if (info->retcode == ERR_SBERR) {
|
|
switch (info->use_ecc) {
|
|
case 1:
|
|
mtd->ecc_stats.corrected++;
|
|
break;
|
|
case 0:
|
|
default:
|
|
break;
|
|
}
|
|
} else if (info->retcode == ERR_DBERR) {
|
|
/*
|
|
* for blank page (all 0xff), HW will calculate its ECC as
|
|
* 0, which is different from the ECC information within
|
|
* OOB, ignore such double bit errors
|
|
*/
|
|
if (is_buf_blank(buf, mtd->writesize))
|
|
mtd->ecc_stats.failed++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
|
|
{
|
|
struct pxa3xx_nand_info *info = mtd->priv;
|
|
char retval = 0xFF;
|
|
|
|
if (info->buf_start < info->buf_count)
|
|
/* Has just send a new command? */
|
|
retval = info->data_buff[info->buf_start++];
|
|
|
|
return retval;
|
|
}
|
|
|
|
static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
|
|
{
|
|
struct pxa3xx_nand_info *info = mtd->priv;
|
|
u16 retval = 0xFFFF;
|
|
|
|
if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
|
|
retval = *((u16 *)(info->data_buff+info->buf_start));
|
|
info->buf_start += 2;
|
|
}
|
|
return retval;
|
|
}
|
|
|
|
static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
|
|
{
|
|
struct pxa3xx_nand_info *info = mtd->priv;
|
|
int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
|
|
|
|
memcpy(buf, info->data_buff + info->buf_start, real_len);
|
|
info->buf_start += real_len;
|
|
}
|
|
|
|
static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
|
|
const uint8_t *buf, int len)
|
|
{
|
|
struct pxa3xx_nand_info *info = mtd->priv;
|
|
int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
|
|
|
|
memcpy(info->data_buff + info->buf_start, buf, real_len);
|
|
info->buf_start += real_len;
|
|
}
|
|
|
|
static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
|
|
const uint8_t *buf, int len)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
|
|
{
|
|
return;
|
|
}
|
|
|
|
static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
|
|
{
|
|
struct pxa3xx_nand_info *info = mtd->priv;
|
|
|
|
/* pxa3xx_nand_send_command has waited for command complete */
|
|
if (this->state == FL_WRITING || this->state == FL_ERASING) {
|
|
if (info->retcode == ERR_NONE)
|
|
return 0;
|
|
else {
|
|
/*
|
|
* any error make it return 0x01 which will tell
|
|
* the caller the erase and write fail
|
|
*/
|
|
return 0x01;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
|
|
const struct pxa3xx_nand_flash *f)
|
|
{
|
|
struct platform_device *pdev = info->pdev;
|
|
struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
|
|
uint32_t ndcr = 0x0; /* enable all interrupts */
|
|
|
|
if (f->page_size != 2048 && f->page_size != 512)
|
|
return -EINVAL;
|
|
|
|
if (f->flash_width != 16 && f->flash_width != 8)
|
|
return -EINVAL;
|
|
|
|
/* calculate flash information */
|
|
info->cmdset = f->cmdset;
|
|
info->page_size = f->page_size;
|
|
info->oob_buff = info->data_buff + f->page_size;
|
|
info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
|
|
|
|
/* calculate addressing information */
|
|
info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
|
|
|
|
if (f->num_blocks * f->page_per_block > 65536)
|
|
info->row_addr_cycles = 3;
|
|
else
|
|
info->row_addr_cycles = 2;
|
|
|
|
ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
|
|
ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
|
|
ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
|
|
ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
|
|
ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
|
|
ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
|
|
|
|
ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
|
|
ndcr |= NDCR_SPARE_EN; /* enable spare by default */
|
|
|
|
info->reg_ndcr = ndcr;
|
|
|
|
pxa3xx_nand_set_timing(info, f->timing);
|
|
return 0;
|
|
}
|
|
|
|
static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
|
|
{
|
|
uint32_t ndcr = nand_readl(info, NDCR);
|
|
struct nand_flash_dev *type = NULL;
|
|
uint32_t id = -1, page_per_block, num_blocks;
|
|
int i;
|
|
|
|
page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
|
|
info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
|
|
/* set info fields needed to read id */
|
|
info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
|
|
info->reg_ndcr = ndcr;
|
|
info->cmdset = &default_cmdset;
|
|
|
|
pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
|
|
id = *((uint16_t *)(info->data_buff));
|
|
if (id == 0)
|
|
return -ENODEV;
|
|
|
|
/* Lookup the flash id */
|
|
for (i = 0; nand_flash_ids[i].name != NULL; i++) {
|
|
if (id == nand_flash_ids[i].id) {
|
|
type = &nand_flash_ids[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!type)
|
|
return -ENODEV;
|
|
|
|
/* fill the missing flash information */
|
|
i = __ffs(page_per_block * info->page_size);
|
|
num_blocks = type->chipsize << (20 - i);
|
|
|
|
/* calculate addressing information */
|
|
info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;
|
|
|
|
if (num_blocks * page_per_block > 65536)
|
|
info->row_addr_cycles = 3;
|
|
else
|
|
info->row_addr_cycles = 2;
|
|
|
|
info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
|
|
info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* the maximum possible buffer size for large page with OOB data
|
|
* is: 2048 + 64 = 2112 bytes, allocate a page here for both the
|
|
* data buffer and the DMA descriptor
|
|
*/
|
|
#define MAX_BUFF_SIZE PAGE_SIZE
|
|
|
|
static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
|
|
{
|
|
struct platform_device *pdev = info->pdev;
|
|
int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
|
|
|
|
if (use_dma == 0) {
|
|
info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
|
|
if (info->data_buff == NULL)
|
|
return -ENOMEM;
|
|
return 0;
|
|
}
|
|
|
|
info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
|
|
&info->data_buff_phys, GFP_KERNEL);
|
|
if (info->data_buff == NULL) {
|
|
dev_err(&pdev->dev, "failed to allocate dma buffer\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
info->data_buff_size = MAX_BUFF_SIZE;
|
|
info->data_desc = (void *)info->data_buff + data_desc_offset;
|
|
info->data_desc_addr = info->data_buff_phys + data_desc_offset;
|
|
|
|
info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
|
|
pxa3xx_nand_data_dma_irq, info);
|
|
if (info->data_dma_ch < 0) {
|
|
dev_err(&pdev->dev, "failed to request data dma\n");
|
|
dma_free_coherent(&pdev->dev, info->data_buff_size,
|
|
info->data_buff, info->data_buff_phys);
|
|
return info->data_dma_ch;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
|
|
{
|
|
struct mtd_info *mtd = info->mtd;
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
/* use the common timing to make a try */
|
|
pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
|
|
chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
|
|
if (info->is_ready)
|
|
return 1;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
static int pxa3xx_nand_scan(struct mtd_info *mtd)
|
|
{
|
|
struct pxa3xx_nand_info *info = mtd->priv;
|
|
struct platform_device *pdev = info->pdev;
|
|
struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
|
|
const struct pxa3xx_nand_flash *f = NULL;
|
|
struct nand_chip *chip = mtd->priv;
|
|
uint32_t id = -1;
|
|
int i, ret, num;
|
|
|
|
if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
|
|
return 0;
|
|
|
|
ret = pxa3xx_nand_sensing(info);
|
|
if (!ret) {
|
|
kfree(mtd);
|
|
info->mtd = NULL;
|
|
printk(KERN_INFO "There is no nand chip on cs 0!\n");
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
|
|
id = *((uint16_t *)(info->data_buff));
|
|
if (id != 0)
|
|
printk(KERN_INFO "Detect a flash id %x\n", id);
|
|
else {
|
|
kfree(mtd);
|
|
info->mtd = NULL;
|
|
printk(KERN_WARNING "Read out ID 0, potential timing set wrong!!\n");
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
|
|
for (i = 0; i < num; i++) {
|
|
if (i < pdata->num_flash)
|
|
f = pdata->flash + i;
|
|
else
|
|
f = &builtin_flash_types[i - pdata->num_flash + 1];
|
|
|
|
/* find the chip in default list */
|
|
if (f->chip_id == id) {
|
|
pxa3xx_nand_config_flash(info, f);
|
|
mtd->writesize = f->page_size;
|
|
mtd->writesize_shift = ffs(mtd->writesize) - 1;
|
|
mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
|
|
mtd->oobsize = mtd->writesize / 32;
|
|
mtd->erasesize = f->page_size * f->page_per_block;
|
|
mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
|
|
mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
|
|
|
|
mtd->name = mtd_names[0];
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash)) {
|
|
kfree(mtd);
|
|
info->mtd = NULL;
|
|
printk(KERN_ERR "ERROR!! flash not defined!!!\n");
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
chip->ecc.mode = NAND_ECC_HW;
|
|
chip->ecc.size = f->page_size;
|
|
chip->chipsize = (uint64_t)f->num_blocks * f->page_per_block
|
|
* f->page_size;
|
|
mtd->size = chip->chipsize;
|
|
|
|
/* Calculate the address shift from the page size */
|
|
chip->page_shift = ffs(mtd->writesize) - 1;
|
|
chip->pagemask = mtd_div_by_ws(chip->chipsize, mtd) - 1;
|
|
chip->numchips = 1;
|
|
chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
|
|
chip->bbt_erase_shift = chip->phys_erase_shift;
|
|
|
|
chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16 : 0;
|
|
chip->options |= NAND_NO_AUTOINCR;
|
|
chip->options |= NAND_NO_READRDY;
|
|
|
|
return nand_scan_tail(mtd);
|
|
}
|
|
|
|
static
|
|
struct pxa3xx_nand_info *alloc_nand_resource(struct platform_device *pdev)
|
|
{
|
|
struct pxa3xx_nand_info *info;
|
|
struct nand_chip *chip;
|
|
struct mtd_info *mtd;
|
|
struct resource *r;
|
|
int ret, irq;
|
|
|
|
mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
|
|
GFP_KERNEL);
|
|
if (!mtd) {
|
|
dev_err(&pdev->dev, "failed to allocate memory\n");
|
|
return NULL;
|
|
}
|
|
|
|
info = (struct pxa3xx_nand_info *)(&mtd[1]);
|
|
chip = (struct nand_chip *)(&mtd[1]);
|
|
info->pdev = pdev;
|
|
info->mtd = mtd;
|
|
mtd->priv = info;
|
|
mtd->owner = THIS_MODULE;
|
|
|
|
chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
|
|
chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
|
|
chip->controller = &info->controller;
|
|
chip->waitfunc = pxa3xx_nand_waitfunc;
|
|
chip->select_chip = pxa3xx_nand_select_chip;
|
|
chip->dev_ready = pxa3xx_nand_dev_ready;
|
|
chip->cmdfunc = pxa3xx_nand_cmdfunc;
|
|
chip->read_word = pxa3xx_nand_read_word;
|
|
chip->read_byte = pxa3xx_nand_read_byte;
|
|
chip->read_buf = pxa3xx_nand_read_buf;
|
|
chip->write_buf = pxa3xx_nand_write_buf;
|
|
chip->verify_buf = pxa3xx_nand_verify_buf;
|
|
|
|
spin_lock_init(&chip->controller->lock);
|
|
init_waitqueue_head(&chip->controller->wq);
|
|
info->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(info->clk)) {
|
|
dev_err(&pdev->dev, "failed to get nand clock\n");
|
|
ret = PTR_ERR(info->clk);
|
|
goto fail_free_mtd;
|
|
}
|
|
clk_enable(info->clk);
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
|
if (r == NULL) {
|
|
dev_err(&pdev->dev, "no resource defined for data DMA\n");
|
|
ret = -ENXIO;
|
|
goto fail_put_clk;
|
|
}
|
|
info->drcmr_dat = r->start;
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
|
|
if (r == NULL) {
|
|
dev_err(&pdev->dev, "no resource defined for command DMA\n");
|
|
ret = -ENXIO;
|
|
goto fail_put_clk;
|
|
}
|
|
info->drcmr_cmd = r->start;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "no IRQ resource defined\n");
|
|
ret = -ENXIO;
|
|
goto fail_put_clk;
|
|
}
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (r == NULL) {
|
|
dev_err(&pdev->dev, "no IO memory resource defined\n");
|
|
ret = -ENODEV;
|
|
goto fail_put_clk;
|
|
}
|
|
|
|
r = request_mem_region(r->start, resource_size(r), pdev->name);
|
|
if (r == NULL) {
|
|
dev_err(&pdev->dev, "failed to request memory resource\n");
|
|
ret = -EBUSY;
|
|
goto fail_put_clk;
|
|
}
|
|
|
|
info->mmio_base = ioremap(r->start, resource_size(r));
|
|
if (info->mmio_base == NULL) {
|
|
dev_err(&pdev->dev, "ioremap() failed\n");
|
|
ret = -ENODEV;
|
|
goto fail_free_res;
|
|
}
|
|
info->mmio_phys = r->start;
|
|
|
|
ret = pxa3xx_nand_init_buff(info);
|
|
if (ret)
|
|
goto fail_free_io;
|
|
|
|
/* initialize all interrupts to be disabled */
|
|
disable_int(info, NDSR_MASK);
|
|
|
|
ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
|
|
pdev->name, info);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to request IRQ\n");
|
|
goto fail_free_buf;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, info);
|
|
|
|
return info;
|
|
|
|
fail_free_buf:
|
|
free_irq(irq, info);
|
|
if (use_dma) {
|
|
pxa_free_dma(info->data_dma_ch);
|
|
dma_free_coherent(&pdev->dev, info->data_buff_size,
|
|
info->data_buff, info->data_buff_phys);
|
|
} else
|
|
kfree(info->data_buff);
|
|
fail_free_io:
|
|
iounmap(info->mmio_base);
|
|
fail_free_res:
|
|
release_mem_region(r->start, resource_size(r));
|
|
fail_put_clk:
|
|
clk_disable(info->clk);
|
|
clk_put(info->clk);
|
|
fail_free_mtd:
|
|
kfree(mtd);
|
|
return NULL;
|
|
}
|
|
|
|
static int pxa3xx_nand_remove(struct platform_device *pdev)
|
|
{
|
|
struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
|
|
struct mtd_info *mtd = info->mtd;
|
|
struct resource *r;
|
|
int irq;
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq >= 0)
|
|
free_irq(irq, info);
|
|
if (use_dma) {
|
|
pxa_free_dma(info->data_dma_ch);
|
|
dma_free_writecombine(&pdev->dev, info->data_buff_size,
|
|
info->data_buff, info->data_buff_phys);
|
|
} else
|
|
kfree(info->data_buff);
|
|
|
|
iounmap(info->mmio_base);
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(r->start, resource_size(r));
|
|
|
|
clk_disable(info->clk);
|
|
clk_put(info->clk);
|
|
|
|
if (mtd) {
|
|
del_mtd_device(mtd);
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
del_mtd_partitions(mtd);
|
|
#endif
|
|
kfree(mtd);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int pxa3xx_nand_probe(struct platform_device *pdev)
|
|
{
|
|
struct pxa3xx_nand_platform_data *pdata;
|
|
struct pxa3xx_nand_info *info;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "no platform data defined\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
info = alloc_nand_resource(pdev);
|
|
if (info == NULL)
|
|
return -ENOMEM;
|
|
|
|
if (pxa3xx_nand_scan(info->mtd)) {
|
|
dev_err(&pdev->dev, "failed to scan nand\n");
|
|
pxa3xx_nand_remove(pdev);
|
|
return -ENODEV;
|
|
}
|
|
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
if (mtd_has_cmdlinepart()) {
|
|
const char *probes[] = { "cmdlinepart", NULL };
|
|
struct mtd_partition *parts;
|
|
int nr_parts;
|
|
|
|
nr_parts = parse_mtd_partitions(info->mtd, probes, &parts, 0);
|
|
|
|
if (nr_parts)
|
|
return add_mtd_partitions(info->mtd, parts, nr_parts);
|
|
}
|
|
|
|
return add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts);
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
|
|
struct mtd_info *mtd = info->mtd;
|
|
|
|
if (info->state) {
|
|
dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
|
|
return -EAGAIN;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pxa3xx_nand_resume(struct platform_device *pdev)
|
|
{
|
|
struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
|
|
struct mtd_info *mtd = info->mtd;
|
|
|
|
nand_writel(info, NDTR0CS0, info->ndtr0cs0);
|
|
nand_writel(info, NDTR1CS0, info->ndtr1cs0);
|
|
clk_enable(info->clk);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define pxa3xx_nand_suspend NULL
|
|
#define pxa3xx_nand_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver pxa3xx_nand_driver = {
|
|
.driver = {
|
|
.name = "pxa3xx-nand",
|
|
},
|
|
.probe = pxa3xx_nand_probe,
|
|
.remove = pxa3xx_nand_remove,
|
|
.suspend = pxa3xx_nand_suspend,
|
|
.resume = pxa3xx_nand_resume,
|
|
};
|
|
|
|
static int __init pxa3xx_nand_init(void)
|
|
{
|
|
return platform_driver_register(&pxa3xx_nand_driver);
|
|
}
|
|
module_init(pxa3xx_nand_init);
|
|
|
|
static void __exit pxa3xx_nand_exit(void)
|
|
{
|
|
platform_driver_unregister(&pxa3xx_nand_driver);
|
|
}
|
|
module_exit(pxa3xx_nand_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("PXA3xx NAND controller driver");
|