49cbe78637
"""The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
31 lines
1,023 B
C
31 lines
1,023 B
C
/*
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* linux/arch/arm/mach-mmp/include/mach/regs-icu.h
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*
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* Interrupt Control Unit
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_ICU_H
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#define __ASM_MACH_ICU_H
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#include <mach/addr-map.h>
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#define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
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#define ICU_REG(x) (ICU_VIRT_BASE + (x))
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#define ICU_INT_CONF(n) ICU_REG((n) << 2)
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#define ICU_INT_CONF_AP_INT (1 << 6)
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#define ICU_INT_CONF_CP_INT (1 << 5)
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#define ICU_INT_CONF_IRQ (1 << 4)
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#define ICU_INT_CONF_MASK (0xf)
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#define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
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#define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
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#define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
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#define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
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#define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
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#endif /* __ASM_MACH_ICU_H */
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