Vladimir Zapolskiy fcde2bf0b9 staging: tidspbridge: MMU2 registers are limited to 32-bit data access ... According to OMAP3 TRM access to MMU registers shall be strictly 32-bit aligned. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>		2011-10-19 13:42:49 -07:00
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core	staging: tidspbridge: fix compilation on dsp clock functions	2011-08-24 14:35:26 -07:00
Documentation
dynload
gen
hw	staging: tidspbridge: MMU2 registers are limited to 32-bit data access	2011-10-19 13:42:49 -07:00
include/dspbridge
pmgr
rmgr
Kconfig
Makefile
TODO