80791be111
Various improvements for configuring the MPC5200 MII link from the device tree: * Look for 'current-speed' property for fixed speed MII links * Look for 'fsl,7-wire-mode' property for boards using the 7 wire mode * move definition of private data structure out of the header file Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Wolfgang Grandegger <wg@grandegger.com>
277 lines
12 KiB
Text
277 lines
12 KiB
Text
MPC5200 Device Tree Bindings
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----------------------------
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(c) 2006-2007 Secret Lab Technologies Ltd
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Grant Likely <grant.likely at secretlab.ca>
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********** DRAFT ***********
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* WARNING: Do not depend on the stability of these bindings just yet.
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* The MPC5200 device tree conventions are still in flux
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* Keep an eye on the linuxppc-dev mailing list for more details
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********** DRAFT ***********
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I - Introduction
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================
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Boards supported by the arch/powerpc architecture require device tree be
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passed by the boot loader to the kernel at boot time. The device tree
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describes what devices are present on the board and how they are
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connected. The device tree can either be passed as a binary blob (as
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described in Documentation/powerpc/booting-without-of.txt), or passed
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by Open Firmware (IEEE 1275) compatible firmware using an OF compatible
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client interface API.
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This document specifies the requirements on the device-tree for mpc5200
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based boards. These requirements are above and beyond the details
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specified in either the Open Firmware spec or booting-without-of.txt
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All new mpc5200-based boards are expected to match this document. In
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cases where this document is not sufficient to support a new board port,
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this document should be updated as part of adding the new board support.
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II - Philosophy
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===============
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The core of this document is naming convention. The whole point of
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defining this convention is to reduce or eliminate the number of
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special cases required to support a 5200 board. If all 5200 boards
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follow the same convention, then generic 5200 support code will work
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rather than coding special cases for each new board.
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This section tries to capture the thought process behind why the naming
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convention is what it is.
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1. names
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---------
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There is strong convention/requirements already established for children
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of the root node. 'cpus' describes the processor cores, 'memory'
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describes memory, and 'chosen' provides boot configuration. Other nodes
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are added to describe devices attached to the processor local bus.
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Following convention already established with other system-on-chip
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processors, 5200 device trees should use the name 'soc5200' for the
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parent node of on chip devices, and the root node should be its parent.
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Child nodes are typically named after the configured function. ie.
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the FEC node is named 'ethernet', and a PSC in uart mode is named 'serial'.
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2. device_type property
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-----------------------
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similar to the node name convention above; the device_type reflects the
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configured function of a device. ie. 'serial' for a uart and 'spi' for
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an spi controller. However, while node names *should* reflect the
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configured function, device_type *must* match the configured function
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exactly.
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3. compatible property
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----------------------
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Since device_type isn't enough to match devices to drivers, there also
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needs to be a naming convention for the compatible property. Compatible
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is an list of device descriptions sorted from specific to generic. For
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the mpc5200, the required format for each compatible value is
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<chip>-<device>[-<mode>]. The OS should be able to match a device driver
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to the device based solely on the compatible value. If two drivers
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match on the compatible list; the 'most compatible' driver should be
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selected.
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The split between the MPC5200 and the MPC5200B leaves a bit of a
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conundrum. How should the compatible property be set up to provide
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maximum compatibility information; but still accurately describe the
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chip? For the MPC5200; the answer is easy. Most of the SoC devices
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originally appeared on the MPC5200. Since they didn't exist anywhere
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else; the 5200 compatible properties will contain only one item;
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"mpc5200-<device>".
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The 5200B is almost the same as the 5200, but not quite. It fixes
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silicon bugs and it adds a small number of enhancements. Most of the
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devices either provide exactly the same interface as on the 5200. A few
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devices have extra functions but still have a backwards compatible mode.
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To express this information as completely as possible, 5200B device trees
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should have two items in the compatible list;
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"mpc5200b-<device>\0mpc5200-<device>". It is *strongly* recommended
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that 5200B device trees follow this convention (instead of only listing
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the base mpc5200 item).
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If another chip appear on the market with one of the mpc5200 SoC
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devices, then the compatible list should include mpc5200-<device>.
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ie. ethernet on mpc5200: compatible = "mpc5200-ethernet"
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ethernet on mpc5200b: compatible = "mpc5200b-ethernet\0mpc5200-ethernet"
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Modal devices, like PSCs, also append the configured function to the
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end of the compatible field. ie. A PSC in i2s mode would specify
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"mpc5200-psc-i2s", not "mpc5200-i2s". This convention is chosen to
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avoid naming conflicts with non-psc devices providing the same
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function. For example, "mpc5200-spi" and "mpc5200-psc-spi" describe
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the mpc5200 simple spi device and a PSC spi mode respectively.
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If the soc device is more generic and present on other SOCs, the
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compatible property can specify the more generic device type also.
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ie. mscan: compatible = "mpc5200-mscan\0fsl,mscan";
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At the time of writing, exact chip may be either 'mpc5200' or
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'mpc5200b'.
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Device drivers should always try to match as generically as possible.
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III - Structure
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===============
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The device tree for an mpc5200 board follows the structure defined in
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booting-without-of.txt with the following additional notes:
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0) the root node
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----------------
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Typical root description node; see booting-without-of
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1) The cpus node
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----------------
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The cpus node follows the basic layout described in booting-without-of.
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The bus-frequency property holds the XLB bus frequency
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The clock-frequency property holds the core frequency
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2) The memory node
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------------------
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Typical memory description node; see booting-without-of.
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3) The soc5200 node
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-------------------
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This node describes the on chip SOC peripherals. Every mpc5200 based
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board will have this node, and as such there is a common naming
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convention for SOC devices.
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Required properties:
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name type description
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---- ---- -----------
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device_type string must be "soc"
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ranges int should be <0 baseaddr baseaddr+10000>
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reg int must be <baseaddr 10000>
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compatible string mpc5200: "mpc5200-soc"
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mpc5200b: "mpc5200b-soc\0mpc5200-soc"
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system-frequency int Fsystem frequency; source of all
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other clocks.
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bus-frequency int IPB bus frequency in HZ. Clock rate
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used by most of the soc devices.
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#interrupt-cells int must be <3>.
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Recommended properties:
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name type description
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---- ---- -----------
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model string Exact model of the chip;
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ie: model="fsl,mpc5200"
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revision string Silicon revision of chip
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ie: revision="M08A"
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The 'model' and 'revision' properties are *strongly* recommended. Having
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them presence acts as a bit of a safety net for working around as yet
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undiscovered bugs on one version of silicon. For example, device drivers
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can use the model and revision properties to decide if a bug fix should
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be turned on.
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4) soc5200 child nodes
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----------------------
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Any on chip SOC devices available to Linux must appear as soc5200 child nodes.
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Note: The tables below show the value for the mpc5200. A mpc5200b device
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tree should use the "mpc5200b-<device>\0mpc5200-<device> form.
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Required soc5200 child nodes:
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name device_type compatible Description
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---- ----------- ---------- -----------
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cdm@<addr> cdm mpc5200-cmd Clock Distribution
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pic@<addr> interrupt-controller mpc5200-pic need an interrupt
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controller to boot
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bestcomm@<addr> dma-controller mpc5200-bestcomm 5200 pic also requires
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the bestcomm device
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Recommended soc5200 child nodes; populate as needed for your board
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name device_type compatible Description
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---- ----------- ---------- -----------
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gpt@<addr> gpt fsl,mpc5200-gpt General purpose timers
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gpt@<addr> gpt fsl,mpc5200-gpt-gpio General purpose
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timers in GPIO mode
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gpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio
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controller
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gpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio
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controller
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rtc@<addr> rtc mpc5200-rtc Real time clock
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mscan@<addr> mscan mpc5200-mscan CAN bus controller
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pci@<addr> pci mpc5200-pci PCI bridge
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serial@<addr> serial mpc5200-psc-uart PSC in serial mode
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i2s@<addr> sound mpc5200-psc-i2s PSC in i2s mode
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ac97@<addr> sound mpc5200-psc-ac97 PSC in ac97 mode
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spi@<addr> spi mpc5200-psc-spi PSC in spi mode
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irda@<addr> irda mpc5200-psc-irda PSC in IrDA mode
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spi@<addr> spi mpc5200-spi MPC5200 spi device
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ethernet@<addr> network mpc5200-fec MPC5200 ethernet device
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ata@<addr> ata mpc5200-ata IDE ATA interface
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i2c@<addr> i2c mpc5200-i2c I2C controller
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usb@<addr> usb-ohci-be mpc5200-ohci,ohci-be USB controller
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xlb@<addr> xlb mpc5200-xlb XLB arbitrator
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Important child node properties
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name type description
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---- ---- -----------
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cell-index int When multiple devices are present, is the
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index of the device in the hardware (ie. There
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are 6 PSC on the 5200 numbered PSC1 to PSC6)
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PSC1 has 'cell-index = <0>'
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PSC4 has 'cell-index = <3>'
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5) General Purpose Timer nodes (child of soc5200 node)
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On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board
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design supports the internal wdt, then the device node for GPT0 should
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include the empty property 'fsl,has-wdt'.
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6) PSC nodes (child of soc5200 node)
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PSC nodes can define the optional 'port-number' property to force assignment
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order of serial ports. For example, PSC5 might be physically connected to
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the port labeled 'COM1' and PSC1 wired to 'COM1'. In this case, PSC5 would
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have a "port-number = <0>" property, and PSC1 would have "port-number = <1>".
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PSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in
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i2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the
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compatible field.
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7) GPIO controller nodes
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Each GPIO controller node should have the empty property gpio-controller and
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#gpio-cells set to 2. First cell is the GPIO number which is interpreted
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according to the bit numbers in the GPIO control registers. The second cell
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is for flags which is currently unsused.
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8) FEC nodes
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The FEC node can specify one of the following properties to configure
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the MII link:
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"fsl,7-wire-mode" - An empty property that specifies the link uses 7-wire
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mode instead of MII
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"current-speed" - Specifies that the MII should be configured for a fixed
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speed. This property should contain two cells. The
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first cell specifies the speed in Mbps and the second
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should be '0' for half duplex and '1' for full duplex
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"phy-handle" - Contains a phandle to an Ethernet PHY.
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IV - Extra Notes
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================
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1. Interrupt mapping
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--------------------
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The mpc5200 pic driver splits hardware IRQ numbers into two levels. The
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split reflects the layout of the PIC hardware itself, which groups
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interrupts into one of three groups; CRIT, MAIN or PERP. Also, the
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Bestcomm dma engine has it's own set of interrupt sources which are
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cascaded off of peripheral interrupt 0, which the driver interprets as a
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fourth group, SDMA.
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The interrupts property for device nodes using the mpc5200 pic consists
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of three cells; <L1 L2 level>
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L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3]
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L2 := interrupt number; directly mapped from the value in the
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"ICTL PerStat, MainStat, CritStat Encoded Register"
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level := [LEVEL_HIGH=0, EDGE_RISING=1, EDGE_FALLING=2, LEVEL_LOW=3]
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2. Shared registers
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-------------------
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Some SoC devices share registers between them. ie. the i2c devices use
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a single clock control register, and almost all device are affected by
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the port_config register. Devices which need to manipulate shared regs
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should look to the parent SoC node. The soc node is responsible
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for arbitrating all shared register access.
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