230 lines
5.5 KiB
C
230 lines
5.5 KiB
C
/*
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* Intel specific MCE features.
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* Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
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* Copyright (C) 2008, 2009 Intel Corporation
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* Author: Andi Kleen
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*/
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#include <linux/gfp.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/sched.h>
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#include <asm/apic.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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#include <asm/mce.h>
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/*
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* Support for Intel Correct Machine Check Interrupts. This allows
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* the CPU to raise an interrupt when a corrected machine check happened.
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* Normally we pick those up using a regular polling timer.
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* Also supports reliable discovery of shared banks.
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*/
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static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
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/*
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* cmci_discover_lock protects against parallel discovery attempts
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* which could race against each other.
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*/
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static DEFINE_RAW_SPINLOCK(cmci_discover_lock);
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#define CMCI_THRESHOLD 1
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static int cmci_supported(int *banks)
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{
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u64 cap;
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if (mce_cmci_disabled || mce_ignore_ce)
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return 0;
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/*
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* Vendor check is not strictly needed, but the initial
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* initialization is vendor keyed and this
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* makes sure none of the backdoors are entered otherwise.
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*/
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
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return 0;
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if (!cpu_has_apic || lapic_get_maxlvt() < 6)
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return 0;
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rdmsrl(MSR_IA32_MCG_CAP, cap);
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*banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
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return !!(cap & MCG_CMCI_P);
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}
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/*
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* The interrupt handler. This is called on every event.
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* Just call the poller directly to log any events.
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* This could in theory increase the threshold under high load,
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* but doesn't for now.
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*/
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static void intel_threshold_interrupt(void)
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{
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machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
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mce_notify_irq();
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}
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static void print_update(char *type, int *hdr, int num)
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{
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if (*hdr == 0)
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printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
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*hdr = 1;
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printk(KERN_CONT " %s:%d", type, num);
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}
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/*
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* Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
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* on this CPU. Use the algorithm recommended in the SDM to discover shared
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* banks.
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*/
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static void cmci_discover(int banks, int boot)
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{
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unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
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unsigned long flags;
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int hdr = 0;
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int i;
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raw_spin_lock_irqsave(&cmci_discover_lock, flags);
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for (i = 0; i < banks; i++) {
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u64 val;
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if (test_bit(i, owned))
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continue;
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rdmsrl(MSR_IA32_MCx_CTL2(i), val);
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/* Already owned by someone else? */
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if (val & MCI_CTL2_CMCI_EN) {
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if (test_and_clear_bit(i, owned) && !boot)
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print_update("SHD", &hdr, i);
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__clear_bit(i, __get_cpu_var(mce_poll_banks));
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continue;
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}
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val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
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val |= MCI_CTL2_CMCI_EN | CMCI_THRESHOLD;
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wrmsrl(MSR_IA32_MCx_CTL2(i), val);
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rdmsrl(MSR_IA32_MCx_CTL2(i), val);
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/* Did the enable bit stick? -- the bank supports CMCI */
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if (val & MCI_CTL2_CMCI_EN) {
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if (!test_and_set_bit(i, owned) && !boot)
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print_update("CMCI", &hdr, i);
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__clear_bit(i, __get_cpu_var(mce_poll_banks));
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} else {
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WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
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}
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}
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raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
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if (hdr)
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printk(KERN_CONT "\n");
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}
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/*
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* Just in case we missed an event during initialization check
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* all the CMCI owned banks.
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*/
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void cmci_recheck(void)
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{
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unsigned long flags;
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int banks;
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if (!mce_available(__this_cpu_ptr(&cpu_info)) || !cmci_supported(&banks))
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return;
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local_irq_save(flags);
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machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
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local_irq_restore(flags);
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}
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/*
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* Disable CMCI on this CPU for all banks it owns when it goes down.
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* This allows other CPUs to claim the banks on rediscovery.
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*/
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void cmci_clear(void)
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{
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unsigned long flags;
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int i;
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int banks;
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u64 val;
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if (!cmci_supported(&banks))
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return;
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raw_spin_lock_irqsave(&cmci_discover_lock, flags);
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for (i = 0; i < banks; i++) {
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if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
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continue;
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/* Disable CMCI */
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rdmsrl(MSR_IA32_MCx_CTL2(i), val);
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val &= ~(MCI_CTL2_CMCI_EN|MCI_CTL2_CMCI_THRESHOLD_MASK);
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wrmsrl(MSR_IA32_MCx_CTL2(i), val);
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__clear_bit(i, __get_cpu_var(mce_banks_owned));
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}
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raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
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}
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/*
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* After a CPU went down cycle through all the others and rediscover
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* Must run in process context.
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*/
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void cmci_rediscover(int dying)
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{
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int banks;
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int cpu;
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cpumask_var_t old;
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if (!cmci_supported(&banks))
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return;
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if (!alloc_cpumask_var(&old, GFP_KERNEL))
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return;
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cpumask_copy(old, ¤t->cpus_allowed);
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for_each_online_cpu(cpu) {
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if (cpu == dying)
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continue;
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if (set_cpus_allowed_ptr(current, cpumask_of(cpu)))
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continue;
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/* Recheck banks in case CPUs don't all have the same */
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if (cmci_supported(&banks))
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cmci_discover(banks, 0);
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}
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set_cpus_allowed_ptr(current, old);
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free_cpumask_var(old);
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}
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/*
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* Reenable CMCI on this CPU in case a CPU down failed.
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*/
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void cmci_reenable(void)
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{
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int banks;
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if (cmci_supported(&banks))
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cmci_discover(banks, 0);
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}
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static void intel_init_cmci(void)
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{
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int banks;
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if (!cmci_supported(&banks))
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return;
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mce_threshold_vector = intel_threshold_interrupt;
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cmci_discover(banks, 1);
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/*
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* For CPU #0 this runs with still disabled APIC, but that's
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* ok because only the vector is set up. We still do another
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* check for the banks later for CPU #0 just to make sure
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* to not miss any events.
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*/
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apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
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cmci_recheck();
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}
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void mce_intel_feature_init(struct cpuinfo_x86 *c)
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{
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intel_init_thermal(c);
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intel_init_cmci();
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}
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