![Tejun Heo](/assets/img/avatar_default.png)
PCI device should be powered up or powered up before its PCI regsiters are accessed. Although PCI configuration register access is allowed in D3hot, PCI device is free to reset its status when transiting from D3hot to D0 causing configuration data to change. Many libata SFF drivers which use ata_pci_init_one() read and update configuration registers before calling ata_pci_init_one() which enables the PCI device. Also, in resume paths, some drivers access registers without resuming the PCI device. This patch adds a call to pcim_enable_device() in init path if register is accessed before calling ata_pci_init_one() and make resume paths first resume PCI devices, access PCI configuration regiters then resume ATA host. While at it... * cmd640 was strange in that it set ->resume even when CONFIG_PM is not. This is by-product of minimal build fix. Updated. * In cs5530, Don't BUG() on reinit failure. Just whine and fail resume. Signed-off-by: Tejun Heo <htejun@gmail.com>
396 lines
10 KiB
C
396 lines
10 KiB
C
/*
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* IDE tuning and bus mastering support for the CS5510/CS5520
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* chipsets
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*
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* The CS5510/CS5520 are slightly unusual devices. Unlike the
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* typical IDE controllers they do bus mastering with the drive in
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* PIO mode and smarter silicon.
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*
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* The practical upshot of this is that we must always tune the
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* drive for the right PIO mode. We must also ignore all the blacklists
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* and the drive bus mastering DMA information. Also to confuse matters
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* further we can do DMA on PIO only drives.
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*
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* DMA on the 5510 also requires we disable_hlt() during DMA on early
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* revisions.
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*
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* *** This driver is strictly experimental ***
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*
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* (c) Copyright Red Hat Inc 2002
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* Documentation:
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* Not publically available.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_cs5520"
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#define DRV_VERSION "0.6.6"
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struct pio_clocks
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{
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int address;
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int assert;
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int recovery;
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};
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static const struct pio_clocks cs5520_pio_clocks[]={
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{3, 6, 11},
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{2, 5, 6},
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{1, 4, 3},
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{1, 3, 2},
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{1, 2, 1}
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};
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/**
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* cs5520_set_timings - program PIO timings
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* @ap: ATA port
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* @adev: ATA device
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*
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* Program the PIO mode timings for the controller according to the pio
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* clocking table.
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*/
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static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int slave = adev->devno;
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pio -= XFER_PIO_0;
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/* Channel command timing */
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pci_write_config_byte(pdev, 0x62 + ap->port_no,
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(cs5520_pio_clocks[pio].recovery << 4) |
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(cs5520_pio_clocks[pio].assert));
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/* FIXME: should these use address ? */
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/* Read command timing */
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pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave,
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(cs5520_pio_clocks[pio].recovery << 4) |
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(cs5520_pio_clocks[pio].assert));
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/* Write command timing */
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pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave,
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(cs5520_pio_clocks[pio].recovery << 4) |
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(cs5520_pio_clocks[pio].assert));
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}
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/**
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* cs5520_enable_dma - turn on DMA bits
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*
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* Turn on the DMA bits for this disk. Needed because the BIOS probably
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* has not done the work for us. Belongs in the core SATA code.
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*/
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static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev)
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{
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/* Set the DMA enable/disable flag */
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u8 reg = ioread8(ap->ioaddr.bmdma_addr + 0x02);
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reg |= 1<<(adev->devno + 5);
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iowrite8(reg, ap->ioaddr.bmdma_addr + 0x02);
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}
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/**
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* cs5520_set_dmamode - program DMA timings
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* @ap: ATA port
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* @adev: ATA device
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*
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* Program the DMA mode timings for the controller according to the pio
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* clocking table. Note that this device sets the DMA timings to PIO
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* mode values. This may seem bizarre but the 5520 architecture talks
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* PIO mode to the disk and DMA mode to the controller so the underlying
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* transfers are PIO timed.
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*/
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static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 };
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cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]);
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cs5520_enable_dma(ap, adev);
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}
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/**
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* cs5520_set_piomode - program PIO timings
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* @ap: ATA port
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* @adev: ATA device
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*
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* Program the PIO mode timings for the controller according to the pio
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* clocking table. We know pio_mode will equal dma_mode because of the
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* CS5520 architecture. At least once we turned DMA on and wrote a
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* mode setter.
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*/
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static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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cs5520_set_timings(ap, adev, adev->pio_mode);
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}
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static struct scsi_host_template cs5520_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_DUMB_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations cs5520_port_ops = {
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.set_piomode = cs5520_set_piomode,
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.set_dmamode = cs5520_set_dmamode,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = ata_cable_40wire,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_dumb_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.port_start = ata_sff_port_start,
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};
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static int __devinit cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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static const unsigned int cmd_port[] = { 0x1F0, 0x170 };
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static const unsigned int ctl_port[] = { 0x3F6, 0x376 };
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struct ata_port_info pi = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = 0x1f,
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.port_ops = &cs5520_port_ops,
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};
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const struct ata_port_info *ppi[2];
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u8 pcicfg;
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void __iomem *iomap[5];
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struct ata_host *host;
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struct ata_ioports *ioaddr;
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int i, rc;
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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/* IDE port enable bits */
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pci_read_config_byte(pdev, 0x60, &pcicfg);
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/* Check if the ATA ports are enabled */
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if ((pcicfg & 3) == 0)
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return -ENODEV;
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ppi[0] = ppi[1] = &ata_dummy_port_info;
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if (pcicfg & 1)
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ppi[0] = π
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if (pcicfg & 2)
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ppi[1] = π
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if ((pcicfg & 0x40) == 0) {
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dev_printk(KERN_WARNING, &pdev->dev,
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"DMA mode disabled. Enabling.\n");
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pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
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}
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pi.mwdma_mask = id->driver_data;
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host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
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if (!host)
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return -ENOMEM;
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/* Perform set up for DMA */
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if (pci_enable_device_io(pdev)) {
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printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
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return -ENODEV;
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}
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if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
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printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
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return -ENODEV;
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}
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if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
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printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
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return -ENODEV;
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}
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/* Map IO ports and initialize host accordingly */
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iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8);
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iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1);
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iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8);
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iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1);
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iomap[4] = pcim_iomap(pdev, 2, 0);
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if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4])
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return -ENOMEM;
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ioaddr = &host->ports[0]->ioaddr;
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ioaddr->cmd_addr = iomap[0];
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ioaddr->ctl_addr = iomap[1];
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ioaddr->altstatus_addr = iomap[1];
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ioaddr->bmdma_addr = iomap[4];
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ata_std_ports(ioaddr);
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ata_port_desc(host->ports[0],
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"cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]);
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ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma");
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ioaddr = &host->ports[1]->ioaddr;
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ioaddr->cmd_addr = iomap[2];
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ioaddr->ctl_addr = iomap[3];
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ioaddr->altstatus_addr = iomap[3];
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ioaddr->bmdma_addr = iomap[4] + 8;
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ata_std_ports(ioaddr);
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ata_port_desc(host->ports[1],
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"cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]);
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ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma");
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/* activate the host */
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pci_set_master(pdev);
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rc = ata_host_start(host);
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if (rc)
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return rc;
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for (i = 0; i < 2; i++) {
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static const int irq[] = { 14, 15 };
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struct ata_port *ap = host->ports[i];
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if (ata_port_is_dummy(ap))
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continue;
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rc = devm_request_irq(&pdev->dev, irq[ap->port_no],
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ata_interrupt, 0, DRV_NAME, host);
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if (rc)
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return rc;
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ata_port_desc(ap, "irq %d", irq[i]);
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}
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return ata_host_register(host, &cs5520_sht);
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}
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#ifdef CONFIG_PM
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/**
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* cs5520_reinit_one - device resume
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* @pdev: PCI device
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*
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* Do any reconfiguration work needed by a resume from RAM. We need
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* to restore DMA mode support on BIOSen which disabled it
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*/
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static int cs5520_reinit_one(struct pci_dev *pdev)
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{
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struct ata_host *host = dev_get_drvdata(&pdev->dev);
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u8 pcicfg;
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int rc;
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rc = ata_pci_device_do_resume(pdev);
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if (rc)
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return rc;
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pci_read_config_byte(pdev, 0x60, &pcicfg);
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if ((pcicfg & 0x40) == 0)
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pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
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ata_host_resume(host);
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return 0;
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}
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/**
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* cs5520_pci_device_suspend - device suspend
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* @pdev: PCI device
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*
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* We have to cut and waste bits from the standard method because
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* the 5520 is a bit odd and not just a pure ATA device. As a result
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* we must not disable it. The needed code is short and this avoids
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* chip specific mess in the core code.
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*/
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static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
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{
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struct ata_host *host = dev_get_drvdata(&pdev->dev);
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int rc = 0;
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rc = ata_host_suspend(host, mesg);
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if (rc)
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return rc;
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pci_save_state(pdev);
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return 0;
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}
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#endif /* CONFIG_PM */
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/* For now keep DMA off. We can set it for all but A rev CS5510 once the
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core ATA code can handle it */
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static const struct pci_device_id pata_cs5520[] = {
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{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
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{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
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{ },
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};
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static struct pci_driver cs5520_pci_driver = {
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.name = DRV_NAME,
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.id_table = pata_cs5520,
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.probe = cs5520_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM
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.suspend = cs5520_pci_device_suspend,
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.resume = cs5520_reinit_one,
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#endif
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};
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static int __init cs5520_init(void)
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{
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return pci_register_driver(&cs5520_pci_driver);
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}
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static void __exit cs5520_exit(void)
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{
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pci_unregister_driver(&cs5520_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, pata_cs5520);
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MODULE_VERSION(DRV_VERSION);
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module_init(cs5520_init);
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module_exit(cs5520_exit);
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