b5166cc252
I discovered that in some cases (PowerMac for example) we wouldn't properly map the PCI IO space on recent kernels. In addition, the code for initializing PCI host bridges was scattered all over the place with some duplication between platforms. This patch fixes the problem and does a small cleanup by creating a pcibios_alloc_controller() in pci_64.c that is similar to the one in pci_32.c (just takes an additional device node argument) that takes care of all the grunt allocation and initialisation work. It should work for both boot time and dynamically allocated PHBs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
98 lines
3 KiB
C
98 lines
3 KiB
C
/*
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* c 2001 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_PPC_PCI_H
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#define _ASM_POWERPC_PPC_PCI_H
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#include <linux/pci.h>
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#include <asm/pci-bridge.h>
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extern unsigned long isa_io_base;
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extern void pci_setup_phb_io(struct pci_controller *hose, int primary);
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extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
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extern struct list_head hose_list;
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extern int global_phb_number;
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extern unsigned long find_and_init_phbs(void);
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extern struct pci_dev *ppc64_isabridge_dev; /* may be NULL if no ISA bus */
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/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
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#define BUID_HI(buid) ((buid) >> 32)
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#define BUID_LO(buid) ((buid) & 0xffffffff)
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/* PCI device_node operations */
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struct device_node;
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typedef void *(*traverse_func)(struct device_node *me, void *data);
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void *traverse_pci_devices(struct device_node *start, traverse_func pre,
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void *data);
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void pci_devs_phb_init(void);
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void pci_devs_phb_init_dynamic(struct pci_controller *phb);
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void __devinit scan_phb(struct pci_controller *hose);
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/* From rtas_pci.h */
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void init_pci_config_tokens (void);
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unsigned long get_phb_buid (struct device_node *);
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/* From pSeries_pci.h */
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extern void pSeries_final_fixup(void);
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extern void pSeries_irq_bus_setup(struct pci_bus *bus);
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extern unsigned long pci_probe_only;
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extern unsigned long pci_assign_all_buses;
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extern int pci_read_irq_line(struct pci_dev *pci_dev);
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/* ---- EEH internal-use-only related routines ---- */
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#ifdef CONFIG_EEH
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/**
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* rtas_set_slot_reset -- unfreeze a frozen slot
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*
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* Clear the EEH-frozen condition on a slot. This routine
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* does this by asserting the PCI #RST line for 1/8th of
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* a second; this routine will sleep while the adapter is
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* being reset.
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*/
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void rtas_set_slot_reset (struct pci_dn *);
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/**
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* eeh_restore_bars - Restore device configuration info.
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*
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* A reset of a PCI device will clear out its config space.
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* This routines will restore the config space for this
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* device, and is children, to values previously obtained
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* from the firmware.
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*/
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void eeh_restore_bars(struct pci_dn *);
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/**
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* rtas_configure_bridge -- firmware initialization of pci bridge
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*
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* Ask the firmware to configure all PCI bridges devices
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* located behind the indicated node. Required after a
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* pci device reset. Does essentially the same hing as
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* eeh_restore_bars, but for brdges, and lets firmware
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* do the work.
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*/
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void rtas_configure_bridge(struct pci_dn *);
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int rtas_write_config(struct pci_dn *, int where, int size, u32 val);
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/**
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* mark and clear slots: find "partition endpoint" PE and set or
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* clear the flags for each subnode of the PE.
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*/
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void eeh_mark_slot (struct device_node *dn, int mode_flag);
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void eeh_clear_slot (struct device_node *dn, int mode_flag);
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#endif
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#endif /* _ASM_POWERPC_PPC_PCI_H */
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