253b0887b3
This moves out the old legacy CPG clocks to their own file, and converts over the existing users. With these clocks going away and each CPU dealing with them on their own, CPUs can gradually move over to the new interface. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
128 lines
2.9 KiB
C
128 lines
2.9 KiB
C
/*
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* arch/sh/kernel/cpu/sh4/clock-shx3.c
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*
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* SH-X3 support for the clock framework
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*
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* Copyright (C) 2006-2007 Renesas Technology Corp.
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* Copyright (C) 2006-2007 Renesas Solutions Corp.
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* Copyright (C) 2006-2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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static int ifc_divisors[] = { 1, 2, 4 ,6 };
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static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
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static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 };
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static int cfc_divisors[] = { 1, 1, 4, 6 };
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#define IFC_POS 28
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#define IFC_MSK 0x0003
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#define BFC_MSK 0x000f
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#define PFC_MSK 0x000f
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#define CFC_MSK 0x0003
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#define BFC_POS 16
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#define PFC_POS 0
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#define CFC_POS 20
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static void master_clk_init(struct clk *clk)
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{
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clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK];
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}
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static struct clk_ops shx3_master_clk_ops = {
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.init = master_clk_init,
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};
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static unsigned long module_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK);
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return clk->parent->rate / pfc_divisors[idx];
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}
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static struct clk_ops shx3_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static unsigned long bus_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK);
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return clk->parent->rate / bfc_divisors[idx];
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}
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static struct clk_ops shx3_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static unsigned long cpu_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
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return clk->parent->rate / ifc_divisors[idx];
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}
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static struct clk_ops shx3_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *shx3_clk_ops[] = {
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&shx3_master_clk_ops,
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&shx3_module_clk_ops,
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&shx3_bus_clk_ops,
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&shx3_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(shx3_clk_ops))
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*ops = shx3_clk_ops[idx];
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}
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static unsigned long shyway_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
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return clk->parent->rate / cfc_divisors[idx];
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}
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static struct clk_ops shx3_shyway_clk_ops = {
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.recalc = shyway_clk_recalc,
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};
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static struct clk shx3_shyway_clk = {
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.name = "shyway_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &shx3_shyway_clk_ops,
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};
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/*
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* Additional SHx3-specific on-chip clocks that aren't already part of the
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* clock framework
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*/
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static struct clk *shx3_onchip_clocks[] = {
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&shx3_shyway_clk,
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};
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int __init arch_clk_init(void)
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{
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
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struct clk *clkp = shx3_onchip_clocks[i];
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clkp->parent = clk;
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ret |= clk_register(clkp);
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}
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clk_put(clk);
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return ret;
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}
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