5e3bcf30d6
The array of pointers is never written, so constify it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
114 lines
3.1 KiB
C
114 lines
3.1 KiB
C
/*
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* the simple DMA Implementation for Blackfin
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*
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* Copyright 2007-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
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(struct dma_register *) DMA1_0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_1_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_2_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_3_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_4_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_5_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_6_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_7_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_8_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_9_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_10_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_11_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_0_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_1_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_2_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_3_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_4_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_5_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_6_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_7_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_8_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_9_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_10_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_11_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
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(struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
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(struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
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(struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
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(struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
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};
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EXPORT_SYMBOL(dma_io_base_addr);
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int channel2irq(unsigned int channel)
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{
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int ret_irq = -1;
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switch (channel) {
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case CH_PPI0:
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ret_irq = IRQ_PPI0;
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break;
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case CH_PPI1:
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ret_irq = IRQ_PPI1;
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break;
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case CH_SPORT0_RX:
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ret_irq = IRQ_SPORT0_RX;
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break;
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case CH_SPORT0_TX:
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ret_irq = IRQ_SPORT0_TX;
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break;
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case CH_SPORT1_RX:
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ret_irq = IRQ_SPORT1_RX;
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break;
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case CH_SPORT1_TX:
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ret_irq = IRQ_SPORT1_TX;
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break;
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case CH_SPI:
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ret_irq = IRQ_SPI;
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break;
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case CH_UART_RX:
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ret_irq = IRQ_UART_RX;
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break;
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case CH_UART_TX:
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ret_irq = IRQ_UART_TX;
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break;
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case CH_MEM_STREAM0_SRC:
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case CH_MEM_STREAM0_DEST:
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ret_irq = IRQ_MEM_DMA0;
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break;
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case CH_MEM_STREAM1_SRC:
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case CH_MEM_STREAM1_DEST:
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ret_irq = IRQ_MEM_DMA1;
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break;
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case CH_MEM_STREAM2_SRC:
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case CH_MEM_STREAM2_DEST:
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ret_irq = IRQ_MEM_DMA2;
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break;
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case CH_MEM_STREAM3_SRC:
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case CH_MEM_STREAM3_DEST:
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ret_irq = IRQ_MEM_DMA3;
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break;
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case CH_IMEM_STREAM0_SRC:
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case CH_IMEM_STREAM0_DEST:
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ret_irq = IRQ_IMEM_DMA0;
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break;
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case CH_IMEM_STREAM1_SRC:
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case CH_IMEM_STREAM1_DEST:
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ret_irq = IRQ_IMEM_DMA1;
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break;
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}
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return ret_irq;
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}
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