d04533650f
The BCM148 has 4 cores but there are also just 4 generic timers available so use the ZBbus cycle counter instead of it. In addition the ZBbus counter also offers a much higher resolution and 64-bit counting so I'm considering a later complete conversion to it once I figure out if all members of the Sibyte SOC family support it - the docs seem to agree but the headers files seem to disagree ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
111 lines
3.4 KiB
C
111 lines
3.4 KiB
C
/*
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* Copyright (C) 2001,2002,2004 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <linux/kernel_stat.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/sibyte/sb1250.h>
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#include <asm/sibyte/bcm1480_regs.h>
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#include <asm/sibyte/bcm1480_int.h>
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extern void smp_call_function_interrupt(void);
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/*
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* These are routines for dealing with the bcm1480 smp capabilities
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* independent of board/firmware
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*/
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static void *mailbox_0_set_regs[] = {
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IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
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IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
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IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
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IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
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};
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static void *mailbox_0_clear_regs[] = {
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IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
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IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
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IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
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IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
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};
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static void *mailbox_0_regs[] = {
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IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
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IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
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IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
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IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
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};
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/*
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* SMP init and finish on secondary CPUs
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*/
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void __cpuinit bcm1480_smp_init(void)
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{
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unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
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STATUSF_IP1 | STATUSF_IP0;
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/* Set interrupt mask, but don't enable */
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change_c0_status(ST0_IM, imask);
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}
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void __cpuinit bcm1480_smp_finish(void)
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{
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extern void sb1480_clockevent_init(void);
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sb1480_clockevent_init();
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local_irq_enable();
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}
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/*
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* These are routines for dealing with the sb1250 smp capabilities
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* independent of board/firmware
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*/
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/*
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* Simple enough; everything is set up, so just poke the appropriate mailbox
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* register, and we should be set
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*/
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void core_send_ipi(int cpu, unsigned int action)
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{
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__raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
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}
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void bcm1480_mailbox_interrupt(void)
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{
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int cpu = smp_processor_id();
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unsigned int action;
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kstat_this_cpu.irqs[K_BCM1480_INT_MBOX_0_0]++;
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/* Load the mailbox register to figure out what we're supposed to do */
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action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff;
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/* Clear the mailbox to clear the interrupt */
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__raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]);
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/*
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* Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the
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* interrupt will do the reschedule for us
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*/
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if (action & SMP_CALL_FUNCTION)
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smp_call_function_interrupt();
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}
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