190 lines
4.4 KiB
C
190 lines
4.4 KiB
C
/**************************************************************************
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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* Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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#ifndef _PSB_DRM_H_
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#define _PSB_DRM_H_
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#define PSB_NUM_PIPE 3
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#define PSB_GPU_ACCESS_READ (1ULL << 32)
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#define PSB_GPU_ACCESS_WRITE (1ULL << 33)
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#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)
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#define PSB_BO_FLAG_COMMAND (1ULL << 52)
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/*
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* Feedback components:
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*/
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struct drm_psb_sizes_arg {
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u32 ta_mem_size;
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u32 mmu_size;
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u32 pds_size;
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u32 rastgeom_size;
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u32 tt_size;
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u32 vram_size;
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};
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struct drm_psb_dpst_lut_arg {
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uint8_t lut[256];
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int output_id;
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};
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#define PSB_DC_CRTC_SAVE 0x01
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#define PSB_DC_CRTC_RESTORE 0x02
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#define PSB_DC_OUTPUT_SAVE 0x04
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#define PSB_DC_OUTPUT_RESTORE 0x08
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#define PSB_DC_CRTC_MASK 0x03
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#define PSB_DC_OUTPUT_MASK 0x0C
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struct drm_psb_dc_state_arg {
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u32 flags;
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u32 obj_id;
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};
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struct drm_psb_mode_operation_arg {
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u32 obj_id;
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u16 operation;
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struct drm_mode_modeinfo mode;
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void *data;
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};
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struct drm_psb_stolen_memory_arg {
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u32 base;
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u32 size;
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};
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/*Display Register Bits*/
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#define REGRWBITS_PFIT_CONTROLS (1 << 0)
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#define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1)
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#define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2)
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#define REGRWBITS_PIPEASRC (1 << 3)
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#define REGRWBITS_PIPEBSRC (1 << 4)
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#define REGRWBITS_VTOTAL_A (1 << 5)
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#define REGRWBITS_VTOTAL_B (1 << 6)
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#define REGRWBITS_DSPACNTR (1 << 8)
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#define REGRWBITS_DSPBCNTR (1 << 9)
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#define REGRWBITS_DSPCCNTR (1 << 10)
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/*Overlay Register Bits*/
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#define OV_REGRWBITS_OVADD (1 << 0)
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#define OV_REGRWBITS_OGAM_ALL (1 << 1)
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#define OVC_REGRWBITS_OVADD (1 << 2)
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#define OVC_REGRWBITS_OGAM_ALL (1 << 3)
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struct drm_psb_register_rw_arg {
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u32 b_force_hw_on;
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u32 display_read_mask;
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u32 display_write_mask;
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struct {
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u32 pfit_controls;
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u32 pfit_autoscale_ratios;
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u32 pfit_programmed_scale_ratios;
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u32 pipeasrc;
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u32 pipebsrc;
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u32 vtotal_a;
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u32 vtotal_b;
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} display;
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u32 overlay_read_mask;
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u32 overlay_write_mask;
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struct {
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u32 OVADD;
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u32 OGAMC0;
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u32 OGAMC1;
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u32 OGAMC2;
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u32 OGAMC3;
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u32 OGAMC4;
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u32 OGAMC5;
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u32 IEP_ENABLED;
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u32 IEP_BLE_MINMAX;
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u32 IEP_BSSCC_CONTROL;
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u32 b_wait_vblank;
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} overlay;
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u32 sprite_enable_mask;
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u32 sprite_disable_mask;
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struct {
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u32 dspa_control;
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u32 dspa_key_value;
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u32 dspa_key_mask;
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u32 dspc_control;
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u32 dspc_stride;
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u32 dspc_position;
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u32 dspc_linear_offset;
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u32 dspc_size;
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u32 dspc_surface;
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} sprite;
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u32 subpicture_enable_mask;
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u32 subpicture_disable_mask;
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};
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/* Controlling the kernel modesetting buffers */
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#define DRM_PSB_KMS_OFF 0x00
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#define DRM_PSB_KMS_ON 0x01
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#define DRM_PSB_SIZES 0x07
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#define DRM_PSB_FUSE_REG 0x08
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#define DRM_PSB_DC_STATE 0x0A
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#define DRM_PSB_ADB 0x0B
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#define DRM_PSB_MODE_OPERATION 0x0C
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#define DRM_PSB_STOLEN_MEMORY 0x0D
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#define DRM_PSB_REGISTER_RW 0x0E
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/**
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* NOTE: Add new commands here, but increment
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* the values below and increment their
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* corresponding defines where they're
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* defined elsewhere.
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*/
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#define DRM_PVR_RESERVED1 0x12
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#define DRM_PVR_RESERVED2 0x13
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#define DRM_PVR_RESERVED3 0x14
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#define DRM_PVR_RESERVED4 0x15
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#define DRM_PVR_RESERVED5 0x16
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#define DRM_PSB_DPST 0x1B
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#define DRM_PSB_GAMMA 0x1C
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#define DRM_PSB_DPST_BL 0x1D
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#define DRM_PVR_RESERVED6 0x1E
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#define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F
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#define PSB_MODE_OPERATION_MODE_VALID 0x01
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#define PSB_MODE_OPERATION_SET_DC_BASE 0x02
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struct drm_psb_get_pipe_from_crtc_id_arg {
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/** ID of CRTC being requested **/
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u32 crtc_id;
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/** pipe of requested CRTC **/
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u32 pipe;
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};
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#endif
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