aaefae9b32
The PF driver needs to remain alert while its ports are down to service requests or errors from virtual functions or FW so keep interrupts and queues available when the ports are brought down. The change makes open_device_map unnecessary so remove it. Signed-off-by: Dimitris Michailidis <dm@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
738 lines
25 KiB
C
738 lines
25 KiB
C
/*
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* This file is part of the Chelsio T4 Ethernet driver for Linux.
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*
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* Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __CXGB4_H__
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#define __CXGB4_H__
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#include <linux/bitops.h>
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#include <linux/cache.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/netdevice.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/timer.h>
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#include <asm/io.h>
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#include "cxgb4_uld.h"
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#include "t4_hw.h"
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#define FW_VERSION_MAJOR 1
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#define FW_VERSION_MINOR 1
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#define FW_VERSION_MICRO 0
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enum {
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MAX_NPORTS = 4, /* max # of ports */
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SERNUM_LEN = 24, /* Serial # length */
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EC_LEN = 16, /* E/C length */
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ID_LEN = 16, /* ID length */
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};
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enum {
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MEM_EDC0,
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MEM_EDC1,
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MEM_MC
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};
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enum dev_master {
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MASTER_CANT,
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MASTER_MAY,
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MASTER_MUST
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};
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enum dev_state {
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DEV_STATE_UNINIT,
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DEV_STATE_INIT,
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DEV_STATE_ERR
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};
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enum {
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PAUSE_RX = 1 << 0,
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PAUSE_TX = 1 << 1,
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PAUSE_AUTONEG = 1 << 2
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};
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struct port_stats {
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u64 tx_octets; /* total # of octets in good frames */
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u64 tx_frames; /* all good frames */
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u64 tx_bcast_frames; /* all broadcast frames */
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u64 tx_mcast_frames; /* all multicast frames */
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u64 tx_ucast_frames; /* all unicast frames */
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u64 tx_error_frames; /* all error frames */
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u64 tx_frames_64; /* # of Tx frames in a particular range */
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u64 tx_frames_65_127;
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u64 tx_frames_128_255;
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u64 tx_frames_256_511;
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u64 tx_frames_512_1023;
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u64 tx_frames_1024_1518;
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u64 tx_frames_1519_max;
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u64 tx_drop; /* # of dropped Tx frames */
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u64 tx_pause; /* # of transmitted pause frames */
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u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
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u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
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u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
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u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
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u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
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u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
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u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
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u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
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u64 rx_octets; /* total # of octets in good frames */
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u64 rx_frames; /* all good frames */
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u64 rx_bcast_frames; /* all broadcast frames */
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u64 rx_mcast_frames; /* all multicast frames */
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u64 rx_ucast_frames; /* all unicast frames */
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u64 rx_too_long; /* # of frames exceeding MTU */
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u64 rx_jabber; /* # of jabber frames */
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u64 rx_fcs_err; /* # of received frames with bad FCS */
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u64 rx_len_err; /* # of received frames with length error */
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u64 rx_symbol_err; /* symbol errors */
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u64 rx_runt; /* # of short frames */
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u64 rx_frames_64; /* # of Rx frames in a particular range */
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u64 rx_frames_65_127;
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u64 rx_frames_128_255;
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u64 rx_frames_256_511;
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u64 rx_frames_512_1023;
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u64 rx_frames_1024_1518;
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u64 rx_frames_1519_max;
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u64 rx_pause; /* # of received pause frames */
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u64 rx_ppp0; /* # of received PPP prio 0 frames */
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u64 rx_ppp1; /* # of received PPP prio 1 frames */
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u64 rx_ppp2; /* # of received PPP prio 2 frames */
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u64 rx_ppp3; /* # of received PPP prio 3 frames */
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u64 rx_ppp4; /* # of received PPP prio 4 frames */
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u64 rx_ppp5; /* # of received PPP prio 5 frames */
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u64 rx_ppp6; /* # of received PPP prio 6 frames */
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u64 rx_ppp7; /* # of received PPP prio 7 frames */
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u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
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u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
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u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
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u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
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u64 rx_trunc0; /* buffer-group 0 truncated packets */
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u64 rx_trunc1; /* buffer-group 1 truncated packets */
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u64 rx_trunc2; /* buffer-group 2 truncated packets */
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u64 rx_trunc3; /* buffer-group 3 truncated packets */
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};
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struct lb_port_stats {
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u64 octets;
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u64 frames;
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u64 bcast_frames;
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u64 mcast_frames;
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u64 ucast_frames;
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u64 error_frames;
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u64 frames_64;
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u64 frames_65_127;
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u64 frames_128_255;
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u64 frames_256_511;
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u64 frames_512_1023;
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u64 frames_1024_1518;
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u64 frames_1519_max;
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u64 drop;
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u64 ovflow0;
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u64 ovflow1;
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u64 ovflow2;
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u64 ovflow3;
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u64 trunc0;
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u64 trunc1;
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u64 trunc2;
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u64 trunc3;
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};
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struct tp_tcp_stats {
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u32 tcpOutRsts;
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u64 tcpInSegs;
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u64 tcpOutSegs;
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u64 tcpRetransSegs;
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};
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struct tp_err_stats {
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u32 macInErrs[4];
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u32 hdrInErrs[4];
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u32 tcpInErrs[4];
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u32 tnlCongDrops[4];
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u32 ofldChanDrops[4];
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u32 tnlTxDrops[4];
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u32 ofldVlanDrops[4];
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u32 tcp6InErrs[4];
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u32 ofldNoNeigh;
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u32 ofldCongDefer;
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};
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struct tp_params {
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unsigned int ntxchan; /* # of Tx channels */
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unsigned int tre; /* log2 of core clocks per TP tick */
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};
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struct vpd_params {
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unsigned int cclk;
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u8 ec[EC_LEN + 1];
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u8 sn[SERNUM_LEN + 1];
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u8 id[ID_LEN + 1];
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};
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struct pci_params {
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unsigned char speed;
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unsigned char width;
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};
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struct adapter_params {
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struct tp_params tp;
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struct vpd_params vpd;
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struct pci_params pci;
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unsigned int fw_vers;
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unsigned int tp_vers;
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u8 api_vers[7];
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unsigned short mtus[NMTUS];
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unsigned short a_wnd[NCCTRL_WIN];
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unsigned short b_wnd[NCCTRL_WIN];
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unsigned char nports; /* # of ethernet ports */
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unsigned char portvec;
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unsigned char rev; /* chip revision */
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unsigned char offload;
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unsigned int ofldq_wr_cred;
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};
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struct trace_params {
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u32 data[TRACE_LEN / 4];
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u32 mask[TRACE_LEN / 4];
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unsigned short snap_len;
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unsigned short min_len;
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unsigned char skip_ofst;
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unsigned char skip_len;
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unsigned char invert;
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unsigned char port;
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};
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struct link_config {
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unsigned short supported; /* link capabilities */
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unsigned short advertising; /* advertised capabilities */
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unsigned short requested_speed; /* speed user has requested */
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unsigned short speed; /* actual link speed */
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unsigned char requested_fc; /* flow control user has requested */
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unsigned char fc; /* actual link flow control */
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unsigned char autoneg; /* autonegotiating? */
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unsigned char link_ok; /* link up? */
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};
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#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
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enum {
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MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
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MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
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MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
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MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
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};
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enum {
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MAX_EGRQ = 128, /* max # of egress queues, including FLs */
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MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
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};
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struct adapter;
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struct vlan_group;
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struct sge_rspq;
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struct port_info {
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struct adapter *adapter;
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struct vlan_group *vlan_grp;
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u16 viid;
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s16 xact_addr_filt; /* index of exact MAC address filter */
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u16 rss_size; /* size of VI's RSS table slice */
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s8 mdio_addr;
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u8 port_type;
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u8 mod_type;
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u8 port_id;
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u8 tx_chan;
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u8 lport; /* associated offload logical port */
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u8 rx_offload; /* CSO, etc */
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u8 nqsets; /* # of qsets */
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u8 first_qset; /* index of first qset */
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struct link_config link_cfg;
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};
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/* port_info.rx_offload flags */
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enum {
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RX_CSO = 1 << 0,
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};
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struct dentry;
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struct work_struct;
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enum { /* adapter flags */
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FULL_INIT_DONE = (1 << 0),
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USING_MSI = (1 << 1),
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USING_MSIX = (1 << 2),
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QUEUES_BOUND = (1 << 3),
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FW_OK = (1 << 4),
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};
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struct rx_sw_desc;
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struct sge_fl { /* SGE free-buffer queue state */
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unsigned int avail; /* # of available Rx buffers */
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unsigned int pend_cred; /* new buffers since last FL DB ring */
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unsigned int cidx; /* consumer index */
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unsigned int pidx; /* producer index */
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unsigned long alloc_failed; /* # of times buffer allocation failed */
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unsigned long large_alloc_failed;
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unsigned long starving;
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/* RO fields */
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unsigned int cntxt_id; /* SGE context id for the free list */
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unsigned int size; /* capacity of free list */
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struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
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__be64 *desc; /* address of HW Rx descriptor ring */
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dma_addr_t addr; /* bus address of HW ring start */
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};
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/* A packet gather list */
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struct pkt_gl {
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skb_frag_t frags[MAX_SKB_FRAGS];
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void *va; /* virtual address of first byte */
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unsigned int nfrags; /* # of fragments */
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unsigned int tot_len; /* total length of fragments */
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};
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typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
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const struct pkt_gl *gl);
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struct sge_rspq { /* state for an SGE response queue */
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struct napi_struct napi;
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const __be64 *cur_desc; /* current descriptor in queue */
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unsigned int cidx; /* consumer index */
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u8 gen; /* current generation bit */
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u8 intr_params; /* interrupt holdoff parameters */
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u8 next_intr_params; /* holdoff params for next interrupt */
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u8 pktcnt_idx; /* interrupt packet threshold */
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u8 uld; /* ULD handling this queue */
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u8 idx; /* queue index within its group */
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int offset; /* offset into current Rx buffer */
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u16 cntxt_id; /* SGE context id for the response q */
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u16 abs_id; /* absolute SGE id for the response q */
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__be64 *desc; /* address of HW response ring */
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dma_addr_t phys_addr; /* physical address of the ring */
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unsigned int iqe_len; /* entry size */
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unsigned int size; /* capacity of response queue */
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struct adapter *adap;
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struct net_device *netdev; /* associated net device */
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rspq_handler_t handler;
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};
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struct sge_eth_stats { /* Ethernet queue statistics */
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unsigned long pkts; /* # of ethernet packets */
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unsigned long lro_pkts; /* # of LRO super packets */
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unsigned long lro_merged; /* # of wire packets merged by LRO */
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unsigned long rx_cso; /* # of Rx checksum offloads */
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unsigned long vlan_ex; /* # of Rx VLAN extractions */
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unsigned long rx_drops; /* # of packets dropped due to no mem */
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};
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struct sge_eth_rxq { /* SW Ethernet Rx queue */
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struct sge_rspq rspq;
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struct sge_fl fl;
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struct sge_eth_stats stats;
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} ____cacheline_aligned_in_smp;
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struct sge_ofld_stats { /* offload queue statistics */
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unsigned long pkts; /* # of packets */
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unsigned long imm; /* # of immediate-data packets */
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unsigned long an; /* # of asynchronous notifications */
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unsigned long nomem; /* # of responses deferred due to no mem */
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};
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struct sge_ofld_rxq { /* SW offload Rx queue */
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struct sge_rspq rspq;
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struct sge_fl fl;
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struct sge_ofld_stats stats;
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} ____cacheline_aligned_in_smp;
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struct tx_desc {
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__be64 flit[8];
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};
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struct tx_sw_desc;
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struct sge_txq {
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unsigned int in_use; /* # of in-use Tx descriptors */
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unsigned int size; /* # of descriptors */
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unsigned int cidx; /* SW consumer index */
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unsigned int pidx; /* producer index */
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unsigned long stops; /* # of times q has been stopped */
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unsigned long restarts; /* # of queue restarts */
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unsigned int cntxt_id; /* SGE context id for the Tx q */
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struct tx_desc *desc; /* address of HW Tx descriptor ring */
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struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
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struct sge_qstat *stat; /* queue status entry */
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dma_addr_t phys_addr; /* physical address of the ring */
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};
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struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
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struct sge_txq q;
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struct netdev_queue *txq; /* associated netdev TX queue */
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unsigned long tso; /* # of TSO requests */
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unsigned long tx_cso; /* # of Tx checksum offloads */
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unsigned long vlan_ins; /* # of Tx VLAN insertions */
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unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
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} ____cacheline_aligned_in_smp;
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struct sge_ofld_txq { /* state for an SGE offload Tx queue */
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struct sge_txq q;
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struct adapter *adap;
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struct sk_buff_head sendq; /* list of backpressured packets */
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struct tasklet_struct qresume_tsk; /* restarts the queue */
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u8 full; /* the Tx ring is full */
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unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
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} ____cacheline_aligned_in_smp;
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struct sge_ctrl_txq { /* state for an SGE control Tx queue */
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struct sge_txq q;
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struct adapter *adap;
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struct sk_buff_head sendq; /* list of backpressured packets */
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struct tasklet_struct qresume_tsk; /* restarts the queue */
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u8 full; /* the Tx ring is full */
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} ____cacheline_aligned_in_smp;
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struct sge {
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struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
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struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
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struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
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struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
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struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
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struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
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struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
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struct sge_rspq intrq ____cacheline_aligned_in_smp;
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spinlock_t intrq_lock;
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u16 max_ethqsets; /* # of available Ethernet queue sets */
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u16 ethqsets; /* # of active Ethernet queue sets */
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u16 ethtxq_rover; /* Tx queue to clean up next */
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u16 ofldqsets; /* # of active offload queue sets */
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u16 rdmaqs; /* # of available RDMA Rx queues */
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u16 ofld_rxq[MAX_OFLD_QSETS];
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u16 rdma_rxq[NCHAN];
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u16 timer_val[SGE_NTIMERS];
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u8 counter_val[SGE_NCOUNTERS];
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unsigned int starve_thres;
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u8 idma_state[2];
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void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
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struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
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DECLARE_BITMAP(starving_fl, MAX_EGRQ);
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DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
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struct timer_list rx_timer; /* refills starving FLs */
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struct timer_list tx_timer; /* checks Tx queues */
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};
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#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
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#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
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#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
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struct l2t_data;
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struct adapter {
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void __iomem *regs;
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struct pci_dev *pdev;
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struct device *pdev_dev;
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unsigned long registered_device_map;
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unsigned long flags;
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|
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const char *name;
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int msg_enable;
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struct adapter_params params;
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struct cxgb4_virt_res vres;
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unsigned int swintr;
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|
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unsigned int wol;
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|
|
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struct {
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unsigned short vec;
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char desc[14];
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} msix_info[MAX_INGQ + 1];
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struct sge sge;
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struct net_device *port[MAX_NPORTS];
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u8 chan_map[NCHAN]; /* channel -> port map */
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struct l2t_data *l2t;
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void *uld_handle[CXGB4_ULD_MAX];
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struct list_head list_node;
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|
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struct tid_info tids;
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void **tid_release_head;
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spinlock_t tid_release_lock;
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struct work_struct tid_release_task;
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bool tid_release_task_busy;
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|
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struct dentry *debugfs_root;
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spinlock_t stats_lock;
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};
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static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
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{
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return readl(adap->regs + reg_addr);
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}
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static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
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{
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writel(val, adap->regs + reg_addr);
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}
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|
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#ifndef readq
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static inline u64 readq(const volatile void __iomem *addr)
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{
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return readl(addr) + ((u64)readl(addr + 4) << 32);
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}
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static inline void writeq(u64 val, volatile void __iomem *addr)
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{
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writel(val, addr);
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writel(val >> 32, addr + 4);
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}
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#endif
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static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
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|
{
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return readq(adap->regs + reg_addr);
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}
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static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
|
|
{
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writeq(val, adap->regs + reg_addr);
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}
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/**
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* netdev2pinfo - return the port_info structure associated with a net_device
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* @dev: the netdev
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|
*
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|
* Return the struct port_info associated with a net_device
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|
*/
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static inline struct port_info *netdev2pinfo(const struct net_device *dev)
|
|
{
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|
return netdev_priv(dev);
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|
}
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|
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/**
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* adap2pinfo - return the port_info of a port
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|
* @adap: the adapter
|
|
* @idx: the port index
|
|
*
|
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* Return the port_info structure for the port of the given index.
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|
*/
|
|
static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
|
|
{
|
|
return netdev_priv(adap->port[idx]);
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|
}
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|
|
|
/**
|
|
* netdev2adap - return the adapter structure associated with a net_device
|
|
* @dev: the netdev
|
|
*
|
|
* Return the struct adapter associated with a net_device
|
|
*/
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|
static inline struct adapter *netdev2adap(const struct net_device *dev)
|
|
{
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|
return netdev2pinfo(dev)->adapter;
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|
}
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|
|
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void t4_os_portmod_changed(const struct adapter *adap, int port_id);
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void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
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|
|
|
void *t4_alloc_mem(size_t size);
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|
void t4_free_mem(void *addr);
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|
|
|
void t4_free_sge_resources(struct adapter *adap);
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|
irq_handler_t t4_intr_handler(struct adapter *adap);
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|
netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
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|
int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
|
|
const struct pkt_gl *gl);
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|
int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
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|
int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
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|
int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
|
|
struct net_device *dev, int intr_idx,
|
|
struct sge_fl *fl, rspq_handler_t hnd);
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|
int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
|
|
struct net_device *dev, struct netdev_queue *netdevq,
|
|
unsigned int iqid);
|
|
int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
|
|
struct net_device *dev, unsigned int iqid,
|
|
unsigned int cmplqid);
|
|
int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
|
|
struct net_device *dev, unsigned int iqid);
|
|
irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
|
|
void t4_sge_init(struct adapter *adap);
|
|
void t4_sge_start(struct adapter *adap);
|
|
void t4_sge_stop(struct adapter *adap);
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|
|
|
#define for_each_port(adapter, iter) \
|
|
for (iter = 0; iter < (adapter)->params.nports; ++iter)
|
|
|
|
static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
|
|
{
|
|
return adap->params.vpd.cclk / 1000;
|
|
}
|
|
|
|
static inline unsigned int us_to_core_ticks(const struct adapter *adap,
|
|
unsigned int us)
|
|
{
|
|
return (us * adap->params.vpd.cclk) / 1000;
|
|
}
|
|
|
|
void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
|
|
u32 val);
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|
|
|
int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
|
|
void *rpl, bool sleep_ok);
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|
|
|
static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
|
|
int size, void *rpl)
|
|
{
|
|
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
|
|
}
|
|
|
|
static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
|
|
int size, void *rpl)
|
|
{
|
|
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
|
|
}
|
|
|
|
void t4_intr_enable(struct adapter *adapter);
|
|
void t4_intr_disable(struct adapter *adapter);
|
|
void t4_intr_clear(struct adapter *adapter);
|
|
int t4_slow_intr_handler(struct adapter *adapter);
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|
|
|
int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
|
|
struct link_config *lc);
|
|
int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
|
|
int t4_seeprom_wp(struct adapter *adapter, bool enable);
|
|
int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
|
|
int t4_check_fw_version(struct adapter *adapter);
|
|
int t4_prep_adapter(struct adapter *adapter);
|
|
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
|
|
void t4_fatal_err(struct adapter *adapter);
|
|
int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
|
|
int filter_index, int enable);
|
|
void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
|
|
int filter_index, int *enabled);
|
|
int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
|
|
int start, int n, const u16 *rspq, unsigned int nrspq);
|
|
int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
|
|
unsigned int flags);
|
|
int t4_read_rss(struct adapter *adapter, u16 *entries);
|
|
int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity);
|
|
int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
|
|
u64 *parity);
|
|
|
|
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
|
|
void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
|
|
|
|
void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
|
|
void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
|
|
void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
|
|
struct tp_tcp_stats *v6);
|
|
void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
|
|
const unsigned short *alpha, const unsigned short *beta);
|
|
|
|
void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
|
|
const u8 *addr);
|
|
int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
|
|
u64 mask0, u64 mask1, unsigned int crc, bool enable);
|
|
|
|
int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
|
|
enum dev_master master, enum dev_state *state);
|
|
int t4_fw_bye(struct adapter *adap, unsigned int mbox);
|
|
int t4_early_init(struct adapter *adap, unsigned int mbox);
|
|
int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
|
|
int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int nparams, const u32 *params,
|
|
u32 *val);
|
|
int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int nparams, const u32 *params,
|
|
const u32 *val);
|
|
int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
|
|
unsigned int rxqi, unsigned int rxq, unsigned int tc,
|
|
unsigned int vi, unsigned int cmask, unsigned int pmask,
|
|
unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
|
|
int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
|
|
unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
|
|
unsigned int *rss_size);
|
|
int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int viid);
|
|
int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
int mtu, int promisc, int all_multi, int bcast, int vlanex,
|
|
bool sleep_ok);
|
|
int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
|
|
unsigned int viid, bool free, unsigned int naddr,
|
|
const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
|
|
int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
int idx, const u8 *addr, bool persist, bool add_smt);
|
|
int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
bool ucast, u64 vec, bool sleep_ok);
|
|
int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
bool rx_en, bool tx_en);
|
|
int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
unsigned int nblinks);
|
|
int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
|
|
unsigned int mmd, unsigned int reg, u16 *valp);
|
|
int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
|
|
unsigned int mmd, unsigned int reg, u16 val);
|
|
int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
|
|
unsigned int pf, unsigned int vf, unsigned int iqid,
|
|
unsigned int fl0id, unsigned int fl1id);
|
|
int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int iqtype, unsigned int iqid,
|
|
unsigned int fl0id, unsigned int fl1id);
|
|
int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int eqid);
|
|
int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int eqid);
|
|
int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int eqid);
|
|
int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
|
|
#endif /* __CXGB4_H__ */
|