5fba096080
Enable cpu_has_clo_clz only when CONFIG_CPU_MIPS32 or CONFIG_CPU_MIPS64
is selected. This will optimize fls() and __fls() to use CLZ insn, and
eventually ffs() and __ffs() as well.
Malta and MIPSSim are development platforms, and need to take care of
various processor configurations, release rivisions and so on, even
across different MIPS ISAs. For such platforms we have to be careful,
for instance, with turning on cpu_has_mips{32,64}r[12] features.
As for CLZ, all MIPS32/64 processors support it, regardless of release
revisions.
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
To: David VomLehn <dvomlehn@cisco.com>
To: macro@linux-mips.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1453/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
70 lines
2 KiB
C
70 lines
2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 2004 Chris Dearman
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
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/*
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* CPU feature overrides for MIPS boards
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*/
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#ifdef CONFIG_CPU_MIPS32
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_4k_cache 1
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/* #define cpu_has_fpu ? */
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/* #define cpu_has_32fpr ? */
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#define cpu_has_counter 1
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/* #define cpu_has_watch ? */
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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/* #define cpu_has_cache_cdex_p ? */
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/* #define cpu_has_cache_cdex_s ? */
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/* #define cpu_has_prefetch ? */
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#define cpu_has_mcheck 1
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/* #define cpu_has_ejtag ? */
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#define cpu_has_llsc 1
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/* #define cpu_has_vtag_icache ? */
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/* #define cpu_has_dc_aliases ? */
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/* #define cpu_has_ic_fills_f_dc ? */
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#define cpu_has_clo_clz 1
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#define cpu_has_nofpuex 0
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/* #define cpu_has_64bits ? */
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/* #define cpu_has_64bit_zero_reg ? */
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/* #define cpu_has_inclusive_pcaches ? */
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#define cpu_icache_snoops_remote_store 1
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#endif
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#ifdef CONFIG_CPU_MIPS64
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_4k_cache 1
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/* #define cpu_has_fpu ? */
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/* #define cpu_has_32fpr ? */
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#define cpu_has_counter 1
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/* #define cpu_has_watch ? */
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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/* #define cpu_has_cache_cdex_p ? */
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/* #define cpu_has_cache_cdex_s ? */
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/* #define cpu_has_prefetch ? */
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#define cpu_has_mcheck 1
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/* #define cpu_has_ejtag ? */
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#define cpu_has_llsc 1
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/* #define cpu_has_vtag_icache ? */
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/* #define cpu_has_dc_aliases ? */
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/* #define cpu_has_ic_fills_f_dc ? */
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#define cpu_has_clo_clz 1
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#define cpu_has_nofpuex 0
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/* #define cpu_has_64bits ? */
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/* #define cpu_has_64bit_zero_reg ? */
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/* #define cpu_has_inclusive_pcaches ? */
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#define cpu_icache_snoops_remote_store 1
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#endif
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#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
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