281b05392f
These changes are all specific to an soc family or the code for one soc. Lots of work for Tegra3 this time, but also a lot of other platforms. There will be another (smaller) set of soc patches later in the merge window for stuff that has dependencies on external trees or that was sent just before the merge window opened. The asoc tree added a few devices to the i.mx platform, which conflict with other devices added in the same place here. The tegra Makefile conflicts between a number of branches, mostly because of changes regarding localtimer.c, which was removed in the end. Signed-off-by: Arnd Bergmann <arnd@arndb.de> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIVAwUAT24+62CrR//JCVInAQLQBQ/8ClDSFYKTkh3XuzryyO3xkiuuj9wp3/av oEzro6HmSFDeWlqyQYYM9nKn6n3zFyyumG7oHt3OyRwrtV742rMOpTK+/Ntj2lFB xUVwKQfu2gEMHvwca3VoXia/pX7knvedEf9bNjeCznkKxQCKCArK2821/2UDGhwx L3/lD70AhpfK0DInNr6HusnZG2pzCdV1tLXUvgs08I68wL7Ps1TDPOLLyTo9dAgf k+E1cpRNLahyiVUBfnp+n3Dg0T+/7iD6zrR7bE9i/zhv6XUcLPt2K5XqYnPuQvzK sHIG8zROmNWzaIzgwYVpJAofi0SHq1OjvA7RtepOq/pGe5QvB9y1RISlpwzBr6Fh 4yuBkeN/Azk0xSHw5w++8L4y/oSSNhB9OWgIZGChZMW33bnHyiZW9mDFJ/PyWD0F kRl++tTuQqDvT5Wx4DXX8RGekIiFq48+MMx3yJjuGarmVsPEvShQCf8TkBbl/KQY /AEXMJTaVTED0R/q+NOY/r4oMFC4JtAVo1ZtTga+N5cYWQCwI9HVSgAKw84Yc1Hj h9r7XjDhmGYFWMfWe9V5NtFNmXl6tAo66fMzSG6+9k+UEXiF1WrhnzBuks5zFU7z z4WBRL0GmaNBdq58dJoM4lucnuhhQk2m7wz5Lt4o17enw0dAfSXQMstDMnbE7c51 65yZh8o9mxs= =WdYR -----END PGP SIGNATURE----- Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull "ARM: SoC specific updates" from Arnd Bergmann: "These changes are all specific to an soc family or the code for one soc. Lots of work for Tegra3 this time, but also a lot of other platforms. There will be another (smaller) set of soc patches later in the merge window for stuff that has dependencies on external trees or that was sent just before the merge window opened. The asoc tree added a few devices to the i.mx platform, which conflict with other devices added in the same place here. The tegra Makefile conflicts between a number of branches, mostly because of changes regarding localtimer.c, which was removed in the end. Signed-off-by: Arnd Bergmann <arnd@arndb.de>" Fix up some trivial conflicts, including the mentioned Tegra Makefile. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (51 commits) ARM: EXYNOS: fix cycle count for periodic mode of clock event timers ARM: EXYNOS: add support JPEG ARM: EXYNOS: Add DMC1, allow PPMU access for DMC ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata() ARM: SAMSUNG: Add __init attribute to samsung_bl_set() ARM: S5PV210: Add usb otg phy control ARM: S3C64XX: Add usb otg phy control ARM: EXYNOS: Enable l2 configuration through device tree ARM: EXYNOS: remove useless code to save/restore L2 ARM: EXYNOS: save L2 settings during bootup ARM: S5P: add L2 early resume code ARM: EXYNOS: Add support AFTR mode on EXYNOS4210 ARM: mx35: Setup the AIPS registers ARM: mx5: Use common function for configuring AIPS ARM: mx3: Setup AIPS registers ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI ARM: defconfig: imx_v6_v7: build in REGULATOR_FIXED_VOLTAGE ARM: imx: update imx_v6_v7_defconfig ARM: tegra: Demote EMC clock inconsistency BUG to WARN ...
235 lines
7.3 KiB
C
235 lines
7.3 KiB
C
/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*
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* Create static mapping between physical to virtual memory.
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include <mach/devices-common.h>
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#include <mach/iomux-v3.h>
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static struct clk *gpc_dvfs_clk;
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static void imx5_idle(void)
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{
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/* gpc clock is needed for SRPG */
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if (gpc_dvfs_clk == NULL) {
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gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
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if (IS_ERR(gpc_dvfs_clk))
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return;
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}
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clk_enable(gpc_dvfs_clk);
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mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
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if (tzic_enable_wake() != 0)
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cpu_do_idle();
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clk_disable(gpc_dvfs_clk);
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}
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/*
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* Define the MX50 memory map.
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*/
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static struct map_desc mx50_io_desc[] __initdata = {
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imx_map_entry(MX50, TZIC, MT_DEVICE),
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imx_map_entry(MX50, SPBA0, MT_DEVICE),
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imx_map_entry(MX50, AIPS1, MT_DEVICE),
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imx_map_entry(MX50, AIPS2, MT_DEVICE),
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};
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/*
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* Define the MX51 memory map.
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*/
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static struct map_desc mx51_io_desc[] __initdata = {
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imx_map_entry(MX51, TZIC, MT_DEVICE),
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imx_map_entry(MX51, IRAM, MT_DEVICE),
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imx_map_entry(MX51, AIPS1, MT_DEVICE),
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imx_map_entry(MX51, SPBA0, MT_DEVICE),
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imx_map_entry(MX51, AIPS2, MT_DEVICE),
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};
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/*
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* Define the MX53 memory map.
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*/
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static struct map_desc mx53_io_desc[] __initdata = {
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imx_map_entry(MX53, TZIC, MT_DEVICE),
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imx_map_entry(MX53, AIPS1, MT_DEVICE),
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imx_map_entry(MX53, SPBA0, MT_DEVICE),
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imx_map_entry(MX53, AIPS2, MT_DEVICE),
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};
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/*
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* This function initializes the memory map. It is called during the
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* system startup to create static physical to virtual memory mappings
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* for the IO modules.
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*/
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void __init mx50_map_io(void)
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{
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iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
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}
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void __init mx51_map_io(void)
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{
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iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
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}
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void __init mx53_map_io(void)
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{
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iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
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}
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void __init imx50_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX50);
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mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
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}
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void __init imx51_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX51);
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mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
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arm_pm_idle = imx5_idle;
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}
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void __init imx53_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX53);
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mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
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}
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void __init mx50_init_irq(void)
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{
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tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
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}
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void __init mx51_init_irq(void)
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{
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tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
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}
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void __init mx53_init_irq(void)
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{
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tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
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}
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static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
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.ap_2_ap_addr = 642,
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.uart_2_mcu_addr = 817,
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.mcu_2_app_addr = 747,
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.mcu_2_shp_addr = 961,
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.ata_2_mcu_addr = 1473,
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.mcu_2_ata_addr = 1392,
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.app_2_per_addr = 1033,
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.app_2_mcu_addr = 683,
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.shp_2_per_addr = 1251,
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.shp_2_mcu_addr = 892,
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};
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static struct sdma_platform_data imx51_sdma_pdata __initdata = {
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.fw_name = "sdma-imx51.bin",
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.script_addrs = &imx51_sdma_script,
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};
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static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
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.ap_2_ap_addr = 642,
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.app_2_mcu_addr = 683,
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.mcu_2_app_addr = 747,
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.uart_2_mcu_addr = 817,
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.shp_2_mcu_addr = 891,
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.mcu_2_shp_addr = 960,
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.uartsh_2_mcu_addr = 1032,
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.spdif_2_mcu_addr = 1100,
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.mcu_2_spdif_addr = 1134,
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.firi_2_mcu_addr = 1193,
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.mcu_2_firi_addr = 1290,
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};
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static struct sdma_platform_data imx53_sdma_pdata __initdata = {
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.fw_name = "sdma-imx53.bin",
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.script_addrs = &imx53_sdma_script,
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};
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static const struct resource imx50_audmux_res[] __initconst = {
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DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
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};
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static const struct resource imx51_audmux_res[] __initconst = {
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DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
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};
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static const struct resource imx53_audmux_res[] __initconst = {
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DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
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};
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void __init imx50_soc_init(void)
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{
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/* i.mx50 has the i.mx31 type gpio */
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mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
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mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
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mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
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mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
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mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
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mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
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/* i.mx50 has the i.mx31 type audmux */
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platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
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ARRAY_SIZE(imx50_audmux_res));
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}
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void __init imx51_soc_init(void)
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{
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/* i.mx51 has the i.mx31 type gpio */
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mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
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mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
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mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
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mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
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/* i.mx51 has the i.mx35 type sdma */
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imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
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/* Setup AIPS registers */
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imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
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imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
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/* i.mx51 has the i.mx31 type audmux */
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platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
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ARRAY_SIZE(imx51_audmux_res));
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}
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void __init imx53_soc_init(void)
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{
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/* i.mx53 has the i.mx31 type gpio */
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mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
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mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
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mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
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mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
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mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
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mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
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mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
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/* i.mx53 has the i.mx35 type sdma */
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imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
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/* Setup AIPS registers */
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imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
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imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
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/* i.mx53 has the i.mx31 type audmux */
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platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
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ARRAY_SIZE(imx53_audmux_res));
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}
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