d427e836d1
ide_find_port() now depends on ->chipset being set for occupied ide_hwifs[] slots so all host drivers have to initialize hwif->chipset properly. This patch fixes a regression on hosts with > 1 port or with a single port but no devices attached to it for an affected host drivers. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
163 lines
3.8 KiB
C
163 lines
3.8 KiB
C
/*
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* Q40 I/O port IDE Driver
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*
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* (c) Richard Zidlicky
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*
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*
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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/*
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* Bases of the IDE interfaces
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*/
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#define Q40IDE_NUM_HWIFS 2
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#define PCIDE_BASE1 0x1f0
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#define PCIDE_BASE2 0x170
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#define PCIDE_BASE3 0x1e8
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#define PCIDE_BASE4 0x168
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#define PCIDE_BASE5 0x1e0
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#define PCIDE_BASE6 0x160
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static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
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PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
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PCIDE_BASE6 */
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};
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static int q40ide_default_irq(unsigned long base)
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{
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switch (base) {
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case 0x1f0: return 14;
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case 0x170: return 15;
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case 0x1e8: return 11;
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default:
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return 0;
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}
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}
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/*
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* Addresses are pretranslated for Q40 ISA access.
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*/
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static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
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ide_ack_intr_t *ack_intr,
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int irq)
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{
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memset(hw, 0, sizeof(hw_regs_t));
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/* BIG FAT WARNING:
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assumption: only DATA port is ever used in 16 bit mode */
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hw->io_ports.data_addr = Q40_ISA_IO_W(base);
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hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
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hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
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hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
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hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
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hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
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hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
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hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
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hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
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hw->irq = irq;
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hw->ack_intr = ack_intr;
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hw->chipset = ide_generic;
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}
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static void q40ide_input_data(ide_drive_t *drive, struct request *rq,
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void *buf, unsigned int len)
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{
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unsigned long data_addr = drive->hwif->io_ports.data_addr;
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if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
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return insw(data_addr, buf, (len + 1) / 2);
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insw_swapw(data_addr, buf, (len + 1) / 2);
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}
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static void q40ide_output_data(ide_drive_t *drive, struct request *rq,
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void *buf, unsigned int len)
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{
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unsigned long data_addr = drive->hwif->io_ports.data_addr;
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if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
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return outsw(data_addr, buf, (len + 1) / 2);
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outsw_swapw(data_addr, buf, (len + 1) / 2);
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}
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/*
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* the static array is needed to have the name reported in /proc/ioports,
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* hwif->name unfortunately isn't available yet
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*/
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static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
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"ide0", "ide1"
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};
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/*
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* Probe for Q40 IDE interfaces
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*/
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static int __init q40ide_init(void)
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{
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int i;
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ide_hwif_t *hwif;
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const char *name;
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u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
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if (!MACH_IS_Q40)
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return -ENODEV;
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printk(KERN_INFO "ide: Q40 IDE controller\n");
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for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
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hw_regs_t hw;
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name = q40_ide_names[i];
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if (!request_region(pcide_bases[i], 8, name)) {
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printk("could not reserve ports %lx-%lx for %s\n",
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pcide_bases[i],pcide_bases[i]+8,name);
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continue;
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}
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if (!request_region(pcide_bases[i]+0x206, 1, name)) {
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printk("could not reserve port %lx for %s\n",
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pcide_bases[i]+0x206,name);
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release_region(pcide_bases[i], 8);
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continue;
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}
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q40_ide_setup_ports(&hw, pcide_bases[i],
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NULL,
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// m68kide_iops,
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q40ide_default_irq(pcide_bases[i]));
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hwif = ide_find_port();
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if (hwif) {
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ide_init_port_data(hwif, hwif->index);
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ide_init_port_hw(hwif, &hw);
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/* Q40 has a byte-swapped IDE interface */
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hwif->input_data = q40ide_input_data;
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hwif->output_data = q40ide_output_data;
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idx[i] = hwif->index;
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}
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}
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ide_device_add(idx, NULL);
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return 0;
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}
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module_init(q40ide_init);
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MODULE_LICENSE("GPL");
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