879999cec9
While ar9170's USB transport packet size is currently set to 8KiB, the PHY is capable of receiving AMPDUs with up to 64KiB. Such a large frame will be split over several rx URBs and exceed the previously allocated space for rx stream reconstruction. This patch increases the buffer size to 64KiB which is in fact the phy & rx stream designed size limit. Cc: stable@kernel.org Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=15591 Reported-by: Christian Mehlis <mehlis@inf.fu-berlin.de> Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
430 lines
14 KiB
C
430 lines
14 KiB
C
/*
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* Atheros AR9170 driver
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*
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* Hardware-specific definitions
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*
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* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, see
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* http://www.gnu.org/licenses/.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* Copyright (c) 2007-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __AR9170_HW_H
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#define __AR9170_HW_H
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#define AR9170_MAX_CMD_LEN 64
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enum ar9170_cmd {
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AR9170_CMD_RREG = 0x00,
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AR9170_CMD_WREG = 0x01,
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AR9170_CMD_RMEM = 0x02,
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AR9170_CMD_WMEM = 0x03,
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AR9170_CMD_BITAND = 0x04,
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AR9170_CMD_BITOR = 0x05,
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AR9170_CMD_EKEY = 0x28,
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AR9170_CMD_DKEY = 0x29,
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AR9170_CMD_FREQUENCY = 0x30,
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AR9170_CMD_RF_INIT = 0x31,
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AR9170_CMD_SYNTH = 0x32,
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AR9170_CMD_FREQ_START = 0x33,
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AR9170_CMD_ECHO = 0x80,
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AR9170_CMD_TALLY = 0x81,
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AR9170_CMD_TALLY_APD = 0x82,
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AR9170_CMD_CONFIG = 0x83,
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AR9170_CMD_RESET = 0x90,
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AR9170_CMD_DKRESET = 0x91,
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AR9170_CMD_DKTX_STATUS = 0x92,
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AR9170_CMD_FDC = 0xA0,
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AR9170_CMD_WREEPROM = 0xB0,
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AR9170_CMD_WFLASH = 0xB0,
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AR9170_CMD_FLASH_ERASE = 0xB1,
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AR9170_CMD_FLASH_PROG = 0xB2,
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AR9170_CMD_FLASH_CHKSUM = 0xB3,
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AR9170_CMD_FLASH_READ = 0xB4,
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AR9170_CMD_FW_DL_INIT = 0xB5,
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AR9170_CMD_MEM_WREEPROM = 0xBB,
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};
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/* endpoints */
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#define AR9170_EP_TX 1
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#define AR9170_EP_RX 2
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#define AR9170_EP_IRQ 3
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#define AR9170_EP_CMD 4
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#define AR9170_EEPROM_START 0x1600
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#define AR9170_GPIO_REG_BASE 0x1d0100
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#define AR9170_GPIO_REG_PORT_TYPE AR9170_GPIO_REG_BASE
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#define AR9170_GPIO_REG_DATA (AR9170_GPIO_REG_BASE + 4)
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#define AR9170_NUM_LEDS 2
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#define AR9170_USB_REG_BASE 0x1e1000
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#define AR9170_USB_REG_DMA_CTL (AR9170_USB_REG_BASE + 0x108)
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#define AR9170_DMA_CTL_ENABLE_TO_DEVICE 0x1
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#define AR9170_DMA_CTL_ENABLE_FROM_DEVICE 0x2
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#define AR9170_DMA_CTL_HIGH_SPEED 0x4
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#define AR9170_DMA_CTL_PACKET_MODE 0x8
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#define AR9170_USB_REG_MAX_AGG_UPLOAD (AR9170_USB_REG_BASE + 0x110)
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#define AR9170_USB_REG_UPLOAD_TIME_CTL (AR9170_USB_REG_BASE + 0x114)
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#define AR9170_MAC_REG_BASE 0x1c3000
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#define AR9170_MAC_REG_TSF_L (AR9170_MAC_REG_BASE + 0x514)
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#define AR9170_MAC_REG_TSF_H (AR9170_MAC_REG_BASE + 0x518)
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#define AR9170_MAC_REG_ATIM_WINDOW (AR9170_MAC_REG_BASE + 0x51C)
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#define AR9170_MAC_REG_BCN_PERIOD (AR9170_MAC_REG_BASE + 0x520)
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#define AR9170_MAC_REG_PRETBTT (AR9170_MAC_REG_BASE + 0x524)
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#define AR9170_MAC_REG_MAC_ADDR_L (AR9170_MAC_REG_BASE + 0x610)
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#define AR9170_MAC_REG_MAC_ADDR_H (AR9170_MAC_REG_BASE + 0x614)
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#define AR9170_MAC_REG_BSSID_L (AR9170_MAC_REG_BASE + 0x618)
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#define AR9170_MAC_REG_BSSID_H (AR9170_MAC_REG_BASE + 0x61c)
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#define AR9170_MAC_REG_GROUP_HASH_TBL_L (AR9170_MAC_REG_BASE + 0x624)
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#define AR9170_MAC_REG_GROUP_HASH_TBL_H (AR9170_MAC_REG_BASE + 0x628)
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#define AR9170_MAC_REG_RX_TIMEOUT (AR9170_MAC_REG_BASE + 0x62C)
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#define AR9170_MAC_REG_BASIC_RATE (AR9170_MAC_REG_BASE + 0x630)
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#define AR9170_MAC_REG_MANDATORY_RATE (AR9170_MAC_REG_BASE + 0x634)
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#define AR9170_MAC_REG_RTS_CTS_RATE (AR9170_MAC_REG_BASE + 0x638)
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#define AR9170_MAC_REG_BACKOFF_PROTECT (AR9170_MAC_REG_BASE + 0x63c)
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#define AR9170_MAC_REG_RX_THRESHOLD (AR9170_MAC_REG_BASE + 0x640)
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#define AR9170_MAC_REG_RX_PE_DELAY (AR9170_MAC_REG_BASE + 0x64C)
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#define AR9170_MAC_REG_DYNAMIC_SIFS_ACK (AR9170_MAC_REG_BASE + 0x658)
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#define AR9170_MAC_REG_SNIFFER (AR9170_MAC_REG_BASE + 0x674)
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#define AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC BIT(0)
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#define AR9170_MAC_REG_SNIFFER_DEFAULTS 0x02000000
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#define AR9170_MAC_REG_ENCRYPTION (AR9170_MAC_REG_BASE + 0x678)
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#define AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE BIT(3)
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#define AR9170_MAC_REG_ENCRYPTION_DEFAULTS 0x70
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#define AR9170_MAC_REG_MISC_680 (AR9170_MAC_REG_BASE + 0x680)
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#define AR9170_MAC_REG_TX_UNDERRUN (AR9170_MAC_REG_BASE + 0x688)
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#define AR9170_MAC_REG_FRAMETYPE_FILTER (AR9170_MAC_REG_BASE + 0x68c)
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#define AR9170_MAC_REG_FTF_ASSOC_REQ BIT(0)
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#define AR9170_MAC_REG_FTF_ASSOC_RESP BIT(1)
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#define AR9170_MAC_REG_FTF_REASSOC_REQ BIT(2)
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#define AR9170_MAC_REG_FTF_REASSOC_RESP BIT(3)
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#define AR9170_MAC_REG_FTF_PRB_REQ BIT(4)
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#define AR9170_MAC_REG_FTF_PRB_RESP BIT(5)
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#define AR9170_MAC_REG_FTF_BIT6 BIT(6)
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#define AR9170_MAC_REG_FTF_BIT7 BIT(7)
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#define AR9170_MAC_REG_FTF_BEACON BIT(8)
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#define AR9170_MAC_REG_FTF_ATIM BIT(9)
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#define AR9170_MAC_REG_FTF_DEASSOC BIT(10)
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#define AR9170_MAC_REG_FTF_AUTH BIT(11)
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#define AR9170_MAC_REG_FTF_DEAUTH BIT(12)
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#define AR9170_MAC_REG_FTF_BIT13 BIT(13)
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#define AR9170_MAC_REG_FTF_BIT14 BIT(14)
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#define AR9170_MAC_REG_FTF_BIT15 BIT(15)
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#define AR9170_MAC_REG_FTF_BAR BIT(24)
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#define AR9170_MAC_REG_FTF_BA BIT(25)
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#define AR9170_MAC_REG_FTF_PSPOLL BIT(26)
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#define AR9170_MAC_REG_FTF_RTS BIT(27)
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#define AR9170_MAC_REG_FTF_CTS BIT(28)
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#define AR9170_MAC_REG_FTF_ACK BIT(29)
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#define AR9170_MAC_REG_FTF_CFE BIT(30)
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#define AR9170_MAC_REG_FTF_CFE_ACK BIT(31)
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#define AR9170_MAC_REG_FTF_DEFAULTS 0x0700ffff
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#define AR9170_MAC_REG_FTF_MONITOR 0xfd00ffff
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#define AR9170_MAC_REG_RX_TOTAL (AR9170_MAC_REG_BASE + 0x6A0)
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#define AR9170_MAC_REG_RX_CRC32 (AR9170_MAC_REG_BASE + 0x6A4)
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#define AR9170_MAC_REG_RX_CRC16 (AR9170_MAC_REG_BASE + 0x6A8)
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#define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI (AR9170_MAC_REG_BASE + 0x6AC)
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#define AR9170_MAC_REG_RX_OVERRUN (AR9170_MAC_REG_BASE + 0x6B0)
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#define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL (AR9170_MAC_REG_BASE + 0x6BC)
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#define AR9170_MAC_REG_TX_RETRY (AR9170_MAC_REG_BASE + 0x6CC)
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#define AR9170_MAC_REG_TX_TOTAL (AR9170_MAC_REG_BASE + 0x6F4)
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#define AR9170_MAC_REG_ACK_EXTENSION (AR9170_MAC_REG_BASE + 0x690)
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#define AR9170_MAC_REG_EIFS_AND_SIFS (AR9170_MAC_REG_BASE + 0x698)
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#define AR9170_MAC_REG_SLOT_TIME (AR9170_MAC_REG_BASE + 0x6F0)
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#define AR9170_MAC_REG_POWERMANAGEMENT (AR9170_MAC_REG_BASE + 0x700)
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#define AR9170_MAC_REG_POWERMGT_IBSS 0xe0
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#define AR9170_MAC_REG_POWERMGT_AP 0xa1
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#define AR9170_MAC_REG_POWERMGT_STA 0x2
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#define AR9170_MAC_REG_POWERMGT_AP_WDS 0x3
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#define AR9170_MAC_REG_POWERMGT_DEFAULTS (0xf << 24)
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#define AR9170_MAC_REG_ROLL_CALL_TBL_L (AR9170_MAC_REG_BASE + 0x704)
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#define AR9170_MAC_REG_ROLL_CALL_TBL_H (AR9170_MAC_REG_BASE + 0x708)
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#define AR9170_MAC_REG_AC0_CW (AR9170_MAC_REG_BASE + 0xB00)
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#define AR9170_MAC_REG_AC1_CW (AR9170_MAC_REG_BASE + 0xB04)
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#define AR9170_MAC_REG_AC2_CW (AR9170_MAC_REG_BASE + 0xB08)
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#define AR9170_MAC_REG_AC3_CW (AR9170_MAC_REG_BASE + 0xB0C)
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#define AR9170_MAC_REG_AC4_CW (AR9170_MAC_REG_BASE + 0xB10)
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#define AR9170_MAC_REG_AC1_AC0_AIFS (AR9170_MAC_REG_BASE + 0xB14)
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#define AR9170_MAC_REG_AC3_AC2_AIFS (AR9170_MAC_REG_BASE + 0xB18)
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#define AR9170_MAC_REG_RETRY_MAX (AR9170_MAC_REG_BASE + 0xB28)
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#define AR9170_MAC_REG_FCS_SELECT (AR9170_MAC_REG_BASE + 0xBB0)
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#define AR9170_MAC_FCS_SWFCS 0x1
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#define AR9170_MAC_FCS_FIFO_PROT 0x4
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#define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND (AR9170_MAC_REG_BASE + 0xB30)
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#define AR9170_MAC_REG_AC1_AC0_TXOP (AR9170_MAC_REG_BASE + 0xB44)
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#define AR9170_MAC_REG_AC3_AC2_TXOP (AR9170_MAC_REG_BASE + 0xB48)
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#define AR9170_MAC_REG_AMPDU_FACTOR (AR9170_MAC_REG_BASE + 0xB9C)
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#define AR9170_MAC_REG_AMPDU_DENSITY (AR9170_MAC_REG_BASE + 0xBA0)
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#define AR9170_MAC_REG_ACK_TABLE (AR9170_MAC_REG_BASE + 0xC00)
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#define AR9170_MAC_REG_AMPDU_RX_THRESH (AR9170_MAC_REG_BASE + 0xC50)
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#define AR9170_MAC_REG_TXRX_MPI (AR9170_MAC_REG_BASE + 0xD7C)
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#define AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f
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#define AR9170_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0
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#define AR9170_MAC_TXRX_MPI_RX_MPI_MASK 0x000f0000
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#define AR9170_MAC_TXRX_MPI_RX_TO_MASK 0xfff00000
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#define AR9170_MAC_REG_BCN_ADDR (AR9170_MAC_REG_BASE + 0xD84)
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#define AR9170_MAC_REG_BCN_LENGTH (AR9170_MAC_REG_BASE + 0xD88)
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#define AR9170_MAC_REG_BCN_PLCP (AR9170_MAC_REG_BASE + 0xD90)
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#define AR9170_MAC_REG_BCN_CTRL (AR9170_MAC_REG_BASE + 0xD94)
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#define AR9170_MAC_REG_BCN_HT1 (AR9170_MAC_REG_BASE + 0xDA0)
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#define AR9170_MAC_REG_BCN_HT2 (AR9170_MAC_REG_BASE + 0xDA4)
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#define AR9170_PWR_REG_BASE 0x1D4000
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#define AR9170_PWR_REG_CLOCK_SEL (AR9170_PWR_REG_BASE + 0x008)
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#define AR9170_PWR_CLK_AHB_40MHZ 0
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#define AR9170_PWR_CLK_AHB_20_22MHZ 1
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#define AR9170_PWR_CLK_AHB_40_44MHZ 2
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#define AR9170_PWR_CLK_AHB_80_88MHZ 3
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#define AR9170_PWR_CLK_DAC_160_INV_DLY 0x70
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/* put beacon here in memory */
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#define AR9170_BEACON_BUFFER_ADDRESS 0x117900
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struct ar9170_tx_control {
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__le16 length;
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__le16 mac_control;
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__le32 phy_control;
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u8 frame_data[0];
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} __packed;
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/* these are either-or */
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#define AR9170_TX_MAC_PROT_RTS 0x0001
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#define AR9170_TX_MAC_PROT_CTS 0x0002
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#define AR9170_TX_MAC_NO_ACK 0x0004
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/* if unset, MAC will only do SIFS space before frame */
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#define AR9170_TX_MAC_BACKOFF 0x0008
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#define AR9170_TX_MAC_BURST 0x0010
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#define AR9170_TX_MAC_AGGR 0x0020
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/* encryption is a two-bit field */
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#define AR9170_TX_MAC_ENCR_NONE 0x0000
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#define AR9170_TX_MAC_ENCR_RC4 0x0040
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#define AR9170_TX_MAC_ENCR_CENC 0x0080
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#define AR9170_TX_MAC_ENCR_AES 0x00c0
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#define AR9170_TX_MAC_MMIC 0x0100
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#define AR9170_TX_MAC_HW_DURATION 0x0200
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#define AR9170_TX_MAC_QOS_SHIFT 10
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#define AR9170_TX_MAC_QOS_MASK (3 << AR9170_TX_MAC_QOS_SHIFT)
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#define AR9170_TX_MAC_AGGR_QOS_BIT1 0x0400
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#define AR9170_TX_MAC_AGGR_QOS_BIT2 0x0800
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#define AR9170_TX_MAC_DISABLE_TXOP 0x1000
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#define AR9170_TX_MAC_TXOP_RIFS 0x2000
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#define AR9170_TX_MAC_IMM_AMPDU 0x4000
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#define AR9170_TX_MAC_RATE_PROBE 0x8000
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/* either-or */
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#define AR9170_TX_PHY_MOD_MASK 0x00000003
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#define AR9170_TX_PHY_MOD_CCK 0x00000000
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#define AR9170_TX_PHY_MOD_OFDM 0x00000001
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#define AR9170_TX_PHY_MOD_HT 0x00000002
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/* depends on modulation */
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#define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004
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#define AR9170_TX_PHY_GREENFIELD 0x00000004
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#define AR9170_TX_PHY_BW_SHIFT 3
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#define AR9170_TX_PHY_BW_MASK (3 << AR9170_TX_PHY_BW_SHIFT)
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#define AR9170_TX_PHY_BW_20MHZ 0
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#define AR9170_TX_PHY_BW_40MHZ 2
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#define AR9170_TX_PHY_BW_40MHZ_DUP 3
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#define AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT 6
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#define AR9170_TX_PHY_TX_HEAVY_CLIP_MASK (7 << AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT)
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#define AR9170_TX_PHY_TX_PWR_SHIFT 9
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#define AR9170_TX_PHY_TX_PWR_MASK (0x3f << AR9170_TX_PHY_TX_PWR_SHIFT)
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/* not part of the hw-spec */
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#define AR9170_TX_PHY_QOS_SHIFT 25
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#define AR9170_TX_PHY_QOS_MASK (3 << AR9170_TX_PHY_QOS_SHIFT)
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#define AR9170_TX_PHY_TXCHAIN_SHIFT 15
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#define AR9170_TX_PHY_TXCHAIN_MASK (7 << AR9170_TX_PHY_TXCHAIN_SHIFT)
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#define AR9170_TX_PHY_TXCHAIN_1 1
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/* use for cck, ofdm 6/9/12/18/24 and HT if capable */
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#define AR9170_TX_PHY_TXCHAIN_2 5
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#define AR9170_TX_PHY_MCS_SHIFT 18
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#define AR9170_TX_PHY_MCS_MASK (0x7f << AR9170_TX_PHY_MCS_SHIFT)
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#define AR9170_TX_PHY_SHORT_GI 0x80000000
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#define AR5416_MAX_RATE_POWER 63
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struct ar9170_rx_head {
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u8 plcp[12];
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} __packed;
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struct ar9170_rx_phystatus {
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union {
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struct {
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u8 rssi_ant0, rssi_ant1, rssi_ant2,
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rssi_ant0x, rssi_ant1x, rssi_ant2x,
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rssi_combined;
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} __packed;
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u8 rssi[7];
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} __packed;
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u8 evm_stream0[6], evm_stream1[6];
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u8 phy_err;
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} __packed;
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struct ar9170_rx_macstatus {
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u8 SAidx, DAidx;
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u8 error;
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u8 status;
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} __packed;
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#define AR9170_ENC_ALG_NONE 0x0
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#define AR9170_ENC_ALG_WEP64 0x1
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#define AR9170_ENC_ALG_TKIP 0x2
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#define AR9170_ENC_ALG_AESCCMP 0x4
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#define AR9170_ENC_ALG_WEP128 0x5
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#define AR9170_ENC_ALG_WEP256 0x6
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#define AR9170_ENC_ALG_CENC 0x7
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#define AR9170_RX_ENC_SOFTWARE 0x8
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static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
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{
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return (t->SAidx & 0xc0) >> 4 |
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(t->DAidx & 0xc0) >> 6;
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}
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#define AR9170_RX_STATUS_MODULATION_MASK 0x03
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#define AR9170_RX_STATUS_MODULATION_CCK 0x00
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#define AR9170_RX_STATUS_MODULATION_OFDM 0x01
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#define AR9170_RX_STATUS_MODULATION_HT 0x02
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#define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03
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|
|
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/* depends on modulation */
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#define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08
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#define AR9170_RX_STATUS_GREENFIELD 0x08
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|
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#define AR9170_RX_STATUS_MPDU_MASK 0x30
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#define AR9170_RX_STATUS_MPDU_SINGLE 0x00
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#define AR9170_RX_STATUS_MPDU_FIRST 0x20
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#define AR9170_RX_STATUS_MPDU_MIDDLE 0x30
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#define AR9170_RX_STATUS_MPDU_LAST 0x10
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#define AR9170_RX_ERROR_RXTO 0x01
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#define AR9170_RX_ERROR_OVERRUN 0x02
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#define AR9170_RX_ERROR_DECRYPT 0x04
|
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#define AR9170_RX_ERROR_FCS 0x08
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#define AR9170_RX_ERROR_WRONG_RA 0x10
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#define AR9170_RX_ERROR_PLCP 0x20
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#define AR9170_RX_ERROR_MMIC 0x40
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#define AR9170_RX_ERROR_FATAL 0x80
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struct ar9170_cmd_tx_status {
|
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u8 dst[ETH_ALEN];
|
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__le32 rate;
|
|
__le16 status;
|
|
} __packed;
|
|
|
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#define AR9170_TX_STATUS_COMPLETE 0x00
|
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#define AR9170_TX_STATUS_RETRY 0x01
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#define AR9170_TX_STATUS_FAILED 0x02
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|
|
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struct ar9170_cmd_ba_failed_count {
|
|
__le16 failed;
|
|
__le16 rate;
|
|
} __packed;
|
|
|
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struct ar9170_cmd_response {
|
|
u8 flag;
|
|
u8 type;
|
|
__le16 padding;
|
|
|
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union {
|
|
struct ar9170_cmd_tx_status tx_status;
|
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struct ar9170_cmd_ba_failed_count ba_fail_cnt;
|
|
u8 data[0];
|
|
};
|
|
} __packed;
|
|
|
|
/* QoS */
|
|
|
|
/* mac80211 queue to HW/FW map */
|
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static const u8 ar9170_qos_hwmap[4] = { 3, 2, 0, 1 };
|
|
|
|
/* HW/FW queue to mac80211 map */
|
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static const u8 ar9170_qos_mac80211map[4] = { 2, 3, 1, 0 };
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|
|
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enum ar9170_txq {
|
|
AR9170_TXQ_BE,
|
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AR9170_TXQ_BK,
|
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AR9170_TXQ_VI,
|
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AR9170_TXQ_VO,
|
|
|
|
__AR9170_NUM_TXQ,
|
|
};
|
|
|
|
#define AR9170_TXQ_DEPTH 32
|
|
#define AR9170_TX_MAX_PENDING 128
|
|
#define AR9170_RX_STREAM_MAX_SIZE 65535
|
|
|
|
#endif /* __AR9170_HW_H */
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