96173a6c4e
- fix PCI interrupt assignment by emulating ioc3 interrupt pin register - use pci_probe_only mode - select correct page size in bridge - remove no longer needed ioc3_sio_init() code [Ralf: Fix for 64kB or larger pagesizes] Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
322 lines
8.5 KiB
C
322 lines
8.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999, 2000, 04, 06 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#include <linux/pci.h>
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#include <asm/paccess.h>
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#include <asm/pci/bridge.h>
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#include <asm/sn/arch.h>
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#include <asm/sn/intr.h>
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#include <asm/sn/sn0/hub.h>
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/*
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* Most of the IOC3 PCI config register aren't present
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* we emulate what is needed for a normal PCI enumeration
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*/
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static u32 emulate_ioc3_cfg(int where, int size)
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{
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if (size == 1 && where == 0x3d)
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return 0x01;
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else if (size == 2 && where == 0x3c)
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return 0x0100;
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else if (size == 4 && where == 0x3c)
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return 0x00000100;
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return 0;
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}
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/*
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* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
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* not really documented, so right now I can't write code which uses it.
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* Therefore we use type 0 accesses for now even though they won't work
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* correcly for PCI-to-PCI bridges.
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*
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* The function is complicated by the ultimate brokeness of the IOC3 chip
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* which is used in SGI systems. The IOC3 can only handle 32-bit PCI
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* accesses and does only decode parts of it's address space.
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*/
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static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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bridge_t *bridge = bc->base;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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volatile void *addr;
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u32 cf, shift, mask;
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int res;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto oh_my_gawd;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
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if (size == 1)
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res = get_dbe(*value, (u8 *) addr);
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else if (size == 2)
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res = get_dbe(*value, (u16 *) addr);
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else
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res = get_dbe(*value, (u32 *) addr);
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return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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oh_my_gawd:
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at the wrong register.
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
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*value = emulate_ioc3_cfg(where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* IOC3 is fucked fucked beyond believe ... Don't try to access
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* anything but 32-bit words ...
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*/
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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*value = (cf >> shift) & mask;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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bridge_t *bridge = bc->base;
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int busno = bus->number;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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volatile void *addr;
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u32 cf, shift, mask;
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int res;
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bridge->b_pci_cfg = (busno << 16) | (slot << 11);
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addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto oh_my_gawd;
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bridge->b_pci_cfg = (busno << 16) | (slot << 11);
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addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
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if (size == 1)
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res = get_dbe(*value, (u8 *) addr);
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else if (size == 2)
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res = get_dbe(*value, (u16 *) addr);
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else
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res = get_dbe(*value, (u32 *) addr);
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return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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oh_my_gawd:
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at the wrong register.
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
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*value = emulate_ioc3_cfg(where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* IOC3 is fucked fucked beyond believe ... Don't try to access
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* anything but 32-bit words ...
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*/
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bridge->b_pci_cfg = (busno << 16) | (slot << 11);
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addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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*value = (cf >> shift) & mask;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * value)
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{
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if (bus->number > 0)
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return pci_conf1_read_config(bus, devfn, where, size, value);
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return pci_conf0_read_config(bus, devfn, where, size, value);
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}
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static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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bridge_t *bridge = bc->base;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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volatile void *addr;
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u32 cf, shift, mask, smask;
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int res;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto oh_my_gawd;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
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if (size == 1) {
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res = put_dbe(value, (u8 *) addr);
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} else if (size == 2) {
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res = put_dbe(value, (u16 *) addr);
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} else {
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res = put_dbe(value, (u32 *) addr);
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}
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if (res)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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oh_my_gawd:
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to touch the wrong register.
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
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return PCIBIOS_SUCCESSFUL;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't try to access
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* anything but 32-bit words ...
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*/
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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smask = mask << shift;
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cf = (cf & ~smask) | ((value & mask) << shift);
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if (put_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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bridge_t *bridge = bc->base;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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int busno = bus->number;
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volatile void *addr;
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u32 cf, shift, mask, smask;
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int res;
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bridge->b_pci_cfg = (busno << 16) | (slot << 11);
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addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto oh_my_gawd;
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addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
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if (size == 1) {
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res = put_dbe(value, (u8 *) addr);
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} else if (size == 2) {
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res = put_dbe(value, (u16 *) addr);
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} else {
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res = put_dbe(value, (u32 *) addr);
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}
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if (res)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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oh_my_gawd:
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/*
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* IOC3 is fucked fucked beyond believe ... Don't even give the
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* generic PCI code a chance to touch the wrong register.
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
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return PCIBIOS_SUCCESSFUL;
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/*
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* IOC3 is fucked fucked beyond believe ... Don't try to access
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* anything but 32-bit words ...
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*/
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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smask = mask << shift;
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cf = (cf & ~smask) | ((value & mask) << shift);
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if (put_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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if (bus->number > 0)
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return pci_conf1_write_config(bus, devfn, where, size, value);
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return pci_conf0_write_config(bus, devfn, where, size, value);
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}
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struct pci_ops bridge_pci_ops = {
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.read = pci_read_config,
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.write = pci_write_config,
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};
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