98a0f86a54
This patch fixes a regression introduced by commit "MIPS: Alchemy: MTX-1:
Use linux gpio api." (bb706b28bb) which broke
PCI bus operation. The problem is caused by alchemy_gpio2_enable() which
resets the GPIO2 block. Two PCI signals (PCI_SERR and PCI_RST) are connected
to GPIO2 and they obviously do not to like the reset. Since GPIO2 is
correctly initialized by the boot monitor (YAMON) it is not necessary to
call this function, so just remove it.
Also replace gpio_set_value() with alchemy_gpio_set_value() to avoid
problems in case gpiolib gets initialized after PCI. And since alchemy
gpio_set_value() calls au_sync() we don't have to au_sync() again later.
Signed-off-by: Bruno Randolf <br1@einfach.org>
To: linux-mips@linux-mips.org
To: manuel.lauss@googlemail.com
Patchwork: https://patchwork.linux-mips.org/patch/1448/
Tested-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
136 lines
4.7 KiB
C
136 lines
4.7 KiB
C
/*
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*
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* BRIEF MODULE DESCRIPTION
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* 4G Systems MTX-1 board setup.
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*
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* Copyright 2003, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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* Bruno Randolf <bruno.randolf@4g-systems.biz>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/pm.h>
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#include <asm/reboot.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <prom.h>
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char irq_tab_alchemy[][5] __initdata = {
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[0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
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[1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
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[2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
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[3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
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[4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
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[5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
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[6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
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[7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
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};
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extern int (*board_pci_idsel)(unsigned int devsel, int assert);
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int mtx1_pci_idsel(unsigned int devsel, int assert);
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static void mtx1_reset(char *c)
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{
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/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
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au_writel(0x00000000, 0xAE00001C);
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}
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static void mtx1_power_off(void)
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{
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printk(KERN_ALERT "It's now safe to remove power\n");
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while (1)
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asm volatile (".set mips3 ; wait ; .set mips1");
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}
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void __init board_setup(void)
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{
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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/* Enable USB power switch */
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alchemy_gpio_direction_output(204, 0);
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#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
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#ifdef CONFIG_PCI
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#if defined(__MIPSEB__)
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au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
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#else
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au_writel(0xf, Au1500_PCI_CFG);
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#endif
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board_pci_idsel = mtx1_pci_idsel;
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#endif
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/* Initialize sys_pinfunc */
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au_writel(SYS_PF_NI2, SYS_PINFUNC);
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/* Initialize GPIO */
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au_writel(0xFFFFFFFF, SYS_TRIOUTCLR);
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alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
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alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
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alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
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alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
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/* Enable LED and set it to green */
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alchemy_gpio_direction_output(211, 1); /* green on */
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alchemy_gpio_direction_output(212, 0); /* red off */
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pm_power_off = mtx1_power_off;
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_machine_halt = mtx1_power_off;
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_machine_restart = mtx1_reset;
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printk(KERN_INFO "4G Systems MTX-1 Board\n");
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}
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int
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mtx1_pci_idsel(unsigned int devsel, int assert)
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{
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#define MTX_IDSEL_ONLY_0_AND_3 0
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#if MTX_IDSEL_ONLY_0_AND_3
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if (devsel != 0 && devsel != 3) {
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printk(KERN_ERR "*** not 0 or 3\n");
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return 0;
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}
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#endif
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if (assert && devsel != 0)
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/* Suppress signal to Cardbus */
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alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
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else
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alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
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udelay(1);
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return 1;
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}
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static int __init mtx1_init_irq(void)
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{
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set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
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set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
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set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
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set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
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set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
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return 0;
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}
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arch_initcall(mtx1_init_irq);
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