Atsushi Nemoto 21e77df215 MIPS: TXx9: Microoptimize interrupt handlers ... The IOC interrupt status register on RBTX49XX only have 8 bits. Use 8-bit version of __fls() to optimize interrupt handlers. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2008-10-11 16:18:47 +01:00
..
boards.h	MIPS: TXx9: Early command-line preprocessing	2008-10-11 16:18:42 +01:00
generic.h	MIPS: TXx9: Microoptimize interrupt handlers	2008-10-11 16:18:47 +01:00
jmr3927.h	[MIPS] TXx9: Make tx3927-specific code more independent	2008-07-30 21:54:39 +01:00
pci.h	[MIPS] TXx9: Add some pci options	2008-07-30 21:54:38 +01:00
rbtx4927.h	MIPS: RBTX4927: More explicit initialization	2008-10-11 16:18:41 +01:00
rbtx4938.h	[MIPS] TXx9: Add 64-bit support	2008-07-20 14:38:21 +01:00
smsc_fdc37m81x.h	MIPS: TXx9: Declare smsc_fdc37m81x_config_get() in smsc_fdc37m81x.h	2008-10-11 16:18:44 +01:00
spi.h	MIPS: TXx9: Make spi_eeprom.c more generic	2008-10-11 16:18:44 +01:00
tx3927.h	MIPS: TXx9: Add mtd support	2008-10-11 16:18:42 +01:00
tx4927.h	MIPS: TXx9: Raise priority of interrupts for errors, timers, SIO	2008-10-11 16:18:43 +01:00
tx4927pcic.h	[MIPS] TXx9: Random cleanup	2008-07-30 21:54:40 +01:00
tx4938.h	MIPS: TXx9: Add mtd support	2008-10-11 16:18:42 +01:00