1555 lines
38 KiB
C
1555 lines
38 KiB
C
/*
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* NVM Express device driver
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* Copyright (c) 2011, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/nvme.h>
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#include <linux/bio.h>
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#include <linux/blkdev.h>
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#include <linux/errno.h>
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#include <linux/fs.h>
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#include <linux/genhd.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kdev_t.h>
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#include <linux/kthread.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pci.h>
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#include <linux/poison.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/version.h>
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#define NVME_Q_DEPTH 1024
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#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
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#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
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#define NVME_MINORS 64
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#define IO_TIMEOUT (5 * HZ)
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#define ADMIN_TIMEOUT (60 * HZ)
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static int nvme_major;
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module_param(nvme_major, int, 0);
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static int use_threaded_interrupts;
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module_param(use_threaded_interrupts, int, 0);
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static DEFINE_SPINLOCK(dev_list_lock);
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static LIST_HEAD(dev_list);
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static struct task_struct *nvme_thread;
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/*
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* Represents an NVM Express device. Each nvme_dev is a PCI function.
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*/
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struct nvme_dev {
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struct list_head node;
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struct nvme_queue **queues;
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u32 __iomem *dbs;
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struct pci_dev *pci_dev;
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struct dma_pool *prp_page_pool;
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struct dma_pool *prp_small_pool;
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int instance;
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int queue_count;
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u32 ctrl_config;
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struct msix_entry *entry;
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struct nvme_bar __iomem *bar;
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struct list_head namespaces;
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char serial[20];
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char model[40];
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char firmware_rev[8];
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};
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/*
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* An NVM Express namespace is equivalent to a SCSI LUN
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*/
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struct nvme_ns {
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struct list_head list;
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struct nvme_dev *dev;
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struct request_queue *queue;
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struct gendisk *disk;
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int ns_id;
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int lba_shift;
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};
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/*
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* An NVM Express queue. Each device has at least two (one for admin
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* commands and one for I/O commands).
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*/
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struct nvme_queue {
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struct device *q_dmadev;
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struct nvme_dev *dev;
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spinlock_t q_lock;
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struct nvme_command *sq_cmds;
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volatile struct nvme_completion *cqes;
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dma_addr_t sq_dma_addr;
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dma_addr_t cq_dma_addr;
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wait_queue_head_t sq_full;
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wait_queue_t sq_cong_wait;
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struct bio_list sq_cong;
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u32 __iomem *q_db;
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u16 q_depth;
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u16 cq_vector;
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u16 sq_head;
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u16 sq_tail;
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u16 cq_head;
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u16 cq_phase;
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unsigned long cmdid_data[];
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};
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/*
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* Check we didin't inadvertently grow the command struct
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*/
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static inline void _nvme_check_size(void)
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{
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BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
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BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
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BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
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}
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struct nvme_cmd_info {
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unsigned long ctx;
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unsigned long timeout;
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};
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static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
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{
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return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
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}
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/**
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* alloc_cmdid - Allocate a Command ID
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* @param nvmeq The queue that will be used for this command
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* @param ctx A pointer that will be passed to the handler
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* @param handler The ID of the handler to call
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*
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* Allocate a Command ID for a queue. The data passed in will
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* be passed to the completion handler. This is implemented by using
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* the bottom two bits of the ctx pointer to store the handler ID.
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* Passing in a pointer that's not 4-byte aligned will cause a BUG.
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* We can change this if it becomes a problem.
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*/
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static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
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unsigned timeout)
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{
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int depth = nvmeq->q_depth;
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struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
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int cmdid;
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BUG_ON((unsigned long)ctx & 3);
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do {
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cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
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if (cmdid >= depth)
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return -EBUSY;
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} while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
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info[cmdid].ctx = (unsigned long)ctx | handler;
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info[cmdid].timeout = jiffies + timeout;
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return cmdid;
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}
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static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
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int handler, unsigned timeout)
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{
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int cmdid;
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wait_event_killable(nvmeq->sq_full,
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(cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
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return (cmdid < 0) ? -EINTR : cmdid;
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}
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/* If you need more than four handlers, you'll need to change how
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* alloc_cmdid and nvme_process_cq work. Consider using a special
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* CMD_CTX value instead, if that works for your situation.
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*/
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enum {
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sync_completion_id = 0,
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bio_completion_id,
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};
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#define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
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#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
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#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
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#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
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static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
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{
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unsigned long data;
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struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
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if (cmdid >= nvmeq->q_depth)
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return CMD_CTX_INVALID;
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data = info[cmdid].ctx;
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info[cmdid].ctx = CMD_CTX_COMPLETED;
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clear_bit(cmdid, nvmeq->cmdid_data);
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wake_up(&nvmeq->sq_full);
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return data;
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}
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static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
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{
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struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
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info[cmdid].ctx = CMD_CTX_CANCELLED;
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}
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static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
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{
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int qid, cpu = get_cpu();
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if (cpu < ns->dev->queue_count)
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qid = cpu + 1;
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else
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qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
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return ns->dev->queues[qid];
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}
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static void put_nvmeq(struct nvme_queue *nvmeq)
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{
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put_cpu();
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}
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/**
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* nvme_submit_cmd: Copy a command into a queue and ring the doorbell
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* @nvmeq: The queue to use
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* @cmd: The command to send
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*
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* Safe to use from interrupt context
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*/
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static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
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{
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unsigned long flags;
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u16 tail;
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/* XXX: Need to check tail isn't going to overrun head */
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spin_lock_irqsave(&nvmeq->q_lock, flags);
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tail = nvmeq->sq_tail;
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memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
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writel(tail, nvmeq->q_db);
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if (++tail == nvmeq->q_depth)
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tail = 0;
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nvmeq->sq_tail = tail;
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spin_unlock_irqrestore(&nvmeq->q_lock, flags);
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return 0;
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}
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struct nvme_prps {
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int npages;
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dma_addr_t first_dma;
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__le64 *list[0];
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};
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static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
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{
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const int last_prp = PAGE_SIZE / 8 - 1;
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int i;
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dma_addr_t prp_dma;
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if (!prps)
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return;
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prp_dma = prps->first_dma;
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if (prps->npages == 0)
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dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
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for (i = 0; i < prps->npages; i++) {
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__le64 *prp_list = prps->list[i];
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dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
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dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
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prp_dma = next_prp_dma;
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}
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kfree(prps);
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}
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struct nvme_bio {
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struct bio *bio;
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int nents;
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struct nvme_prps *prps;
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struct scatterlist sg[0];
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};
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/* XXX: use a mempool */
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static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
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{
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return kzalloc(sizeof(struct nvme_bio) +
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sizeof(struct scatterlist) * nseg, gfp);
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}
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static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
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{
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nvme_free_prps(nvmeq->dev, nbio->prps);
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kfree(nbio);
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}
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static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
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struct nvme_completion *cqe)
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{
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struct nvme_bio *nbio = ctx;
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struct bio *bio = nbio->bio;
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u16 status = le16_to_cpup(&cqe->status) >> 1;
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dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
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bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
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free_nbio(nvmeq, nbio);
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bio_endio(bio, status ? -EIO : 0);
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}
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/* length is in bytes */
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static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
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struct nvme_common_command *cmd,
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struct scatterlist *sg, int length)
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{
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struct dma_pool *pool;
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int dma_len = sg_dma_len(sg);
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u64 dma_addr = sg_dma_address(sg);
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int offset = offset_in_page(dma_addr);
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__le64 *prp_list;
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dma_addr_t prp_dma;
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int nprps, npages, i, prp_page;
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struct nvme_prps *prps = NULL;
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cmd->prp1 = cpu_to_le64(dma_addr);
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length -= (PAGE_SIZE - offset);
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if (length <= 0)
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return prps;
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dma_len -= (PAGE_SIZE - offset);
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if (dma_len) {
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dma_addr += (PAGE_SIZE - offset);
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} else {
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sg = sg_next(sg);
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dma_addr = sg_dma_address(sg);
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dma_len = sg_dma_len(sg);
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}
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if (length <= PAGE_SIZE) {
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cmd->prp2 = cpu_to_le64(dma_addr);
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return prps;
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}
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nprps = DIV_ROUND_UP(length, PAGE_SIZE);
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npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
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prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
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prp_page = 0;
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if (nprps <= (256 / 8)) {
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pool = dev->prp_small_pool;
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prps->npages = 0;
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} else {
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pool = dev->prp_page_pool;
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prps->npages = npages;
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}
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prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
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prps->list[prp_page++] = prp_list;
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prps->first_dma = prp_dma;
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cmd->prp2 = cpu_to_le64(prp_dma);
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i = 0;
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for (;;) {
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if (i == PAGE_SIZE / 8 - 1) {
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__le64 *old_prp_list = prp_list;
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prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
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prps->list[prp_page++] = prp_list;
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old_prp_list[i] = cpu_to_le64(prp_dma);
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i = 0;
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}
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prp_list[i++] = cpu_to_le64(dma_addr);
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dma_len -= PAGE_SIZE;
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dma_addr += PAGE_SIZE;
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length -= PAGE_SIZE;
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if (length <= 0)
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break;
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if (dma_len > 0)
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continue;
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BUG_ON(dma_len < 0);
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sg = sg_next(sg);
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dma_addr = sg_dma_address(sg);
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dma_len = sg_dma_len(sg);
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}
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return prps;
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}
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static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
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struct bio *bio, enum dma_data_direction dma_dir, int psegs)
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{
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struct bio_vec *bvec, *bvprv = NULL;
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struct scatterlist *sg = NULL;
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int i, nsegs = 0;
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|
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sg_init_table(nbio->sg, psegs);
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bio_for_each_segment(bvec, bio, i) {
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if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
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sg->length += bvec->bv_len;
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} else {
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/* Check bvprv && offset == 0 */
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sg = sg ? sg + 1 : nbio->sg;
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sg_set_page(sg, bvec->bv_page, bvec->bv_len,
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bvec->bv_offset);
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nsegs++;
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}
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bvprv = bvec;
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}
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nbio->nents = nsegs;
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sg_mark_end(sg);
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return dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir);
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}
|
|
|
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static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
|
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struct bio *bio)
|
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{
|
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struct nvme_command *cmnd;
|
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struct nvme_bio *nbio;
|
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enum dma_data_direction dma_dir;
|
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int cmdid, result = -ENOMEM;
|
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u16 control;
|
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u32 dsmgmt;
|
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int psegs = bio_phys_segments(ns->queue, bio);
|
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|
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nbio = alloc_nbio(psegs, GFP_ATOMIC);
|
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if (!nbio)
|
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goto nomem;
|
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nbio->bio = bio;
|
|
|
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result = -EBUSY;
|
|
cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
|
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if (unlikely(cmdid < 0))
|
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goto free_nbio;
|
|
|
|
control = 0;
|
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if (bio->bi_rw & REQ_FUA)
|
|
control |= NVME_RW_FUA;
|
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if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
|
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control |= NVME_RW_LR;
|
|
|
|
dsmgmt = 0;
|
|
if (bio->bi_rw & REQ_RAHEAD)
|
|
dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
|
|
|
|
cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
|
|
|
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memset(cmnd, 0, sizeof(*cmnd));
|
|
if (bio_data_dir(bio)) {
|
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cmnd->rw.opcode = nvme_cmd_write;
|
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dma_dir = DMA_TO_DEVICE;
|
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} else {
|
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cmnd->rw.opcode = nvme_cmd_read;
|
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dma_dir = DMA_FROM_DEVICE;
|
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}
|
|
|
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result = -ENOMEM;
|
|
if (nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs) == 0)
|
|
goto free_nbio;
|
|
|
|
cmnd->rw.flags = 1;
|
|
cmnd->rw.command_id = cmdid;
|
|
cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
|
|
nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
|
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bio->bi_size);
|
|
cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
|
|
cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
|
|
cmnd->rw.control = cpu_to_le16(control);
|
|
cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
|
|
|
|
writel(nvmeq->sq_tail, nvmeq->q_db);
|
|
if (++nvmeq->sq_tail == nvmeq->q_depth)
|
|
nvmeq->sq_tail = 0;
|
|
|
|
return 0;
|
|
|
|
free_nbio:
|
|
free_nbio(nvmeq, nbio);
|
|
nomem:
|
|
return result;
|
|
}
|
|
|
|
/*
|
|
* NB: return value of non-zero would mean that we were a stacking driver.
|
|
* make_request must always succeed.
|
|
*/
|
|
static int nvme_make_request(struct request_queue *q, struct bio *bio)
|
|
{
|
|
struct nvme_ns *ns = q->queuedata;
|
|
struct nvme_queue *nvmeq = get_nvmeq(ns);
|
|
int result = -EBUSY;
|
|
|
|
spin_lock_irq(&nvmeq->q_lock);
|
|
if (bio_list_empty(&nvmeq->sq_cong))
|
|
result = nvme_submit_bio_queue(nvmeq, ns, bio);
|
|
if (unlikely(result)) {
|
|
if (bio_list_empty(&nvmeq->sq_cong))
|
|
add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
|
|
bio_list_add(&nvmeq->sq_cong, bio);
|
|
}
|
|
|
|
spin_unlock_irq(&nvmeq->q_lock);
|
|
put_nvmeq(nvmeq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct sync_cmd_info {
|
|
struct task_struct *task;
|
|
u32 result;
|
|
int status;
|
|
};
|
|
|
|
static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
|
|
struct nvme_completion *cqe)
|
|
{
|
|
struct sync_cmd_info *cmdinfo = ctx;
|
|
if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
|
|
return;
|
|
if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
|
|
dev_warn(nvmeq->q_dmadev,
|
|
"completed id %d twice on queue %d\n",
|
|
cqe->command_id, le16_to_cpup(&cqe->sq_id));
|
|
return;
|
|
}
|
|
if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
|
|
dev_warn(nvmeq->q_dmadev,
|
|
"invalid id %d completed on queue %d\n",
|
|
cqe->command_id, le16_to_cpup(&cqe->sq_id));
|
|
return;
|
|
}
|
|
cmdinfo->result = le32_to_cpup(&cqe->result);
|
|
cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
|
|
wake_up_process(cmdinfo->task);
|
|
}
|
|
|
|
typedef void (*completion_fn)(struct nvme_queue *, void *,
|
|
struct nvme_completion *);
|
|
|
|
static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
|
|
{
|
|
u16 head, phase;
|
|
|
|
static const completion_fn completions[4] = {
|
|
[sync_completion_id] = sync_completion,
|
|
[bio_completion_id] = bio_completion,
|
|
};
|
|
|
|
head = nvmeq->cq_head;
|
|
phase = nvmeq->cq_phase;
|
|
|
|
for (;;) {
|
|
unsigned long data;
|
|
void *ptr;
|
|
unsigned char handler;
|
|
struct nvme_completion cqe = nvmeq->cqes[head];
|
|
if ((le16_to_cpu(cqe.status) & 1) != phase)
|
|
break;
|
|
nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
|
|
if (++head == nvmeq->q_depth) {
|
|
head = 0;
|
|
phase = !phase;
|
|
}
|
|
|
|
data = free_cmdid(nvmeq, cqe.command_id);
|
|
handler = data & 3;
|
|
ptr = (void *)(data & ~3UL);
|
|
completions[handler](nvmeq, ptr, &cqe);
|
|
}
|
|
|
|
/* If the controller ignores the cq head doorbell and continuously
|
|
* writes to the queue, it is theoretically possible to wrap around
|
|
* the queue twice and mistakenly return IRQ_NONE. Linux only
|
|
* requires that 0.1% of your interrupts are handled, so this isn't
|
|
* a big problem.
|
|
*/
|
|
if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
|
|
return IRQ_NONE;
|
|
|
|
writel(head, nvmeq->q_db + 1);
|
|
nvmeq->cq_head = head;
|
|
nvmeq->cq_phase = phase;
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t nvme_irq(int irq, void *data)
|
|
{
|
|
irqreturn_t result;
|
|
struct nvme_queue *nvmeq = data;
|
|
spin_lock(&nvmeq->q_lock);
|
|
result = nvme_process_cq(nvmeq);
|
|
spin_unlock(&nvmeq->q_lock);
|
|
return result;
|
|
}
|
|
|
|
static irqreturn_t nvme_irq_check(int irq, void *data)
|
|
{
|
|
struct nvme_queue *nvmeq = data;
|
|
struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
|
|
if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
|
|
return IRQ_NONE;
|
|
return IRQ_WAKE_THREAD;
|
|
}
|
|
|
|
static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
|
|
{
|
|
spin_lock_irq(&nvmeq->q_lock);
|
|
cancel_cmdid_data(nvmeq, cmdid);
|
|
spin_unlock_irq(&nvmeq->q_lock);
|
|
}
|
|
|
|
/*
|
|
* Returns 0 on success. If the result is negative, it's a Linux error code;
|
|
* if the result is positive, it's an NVM Express status code
|
|
*/
|
|
static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
|
|
struct nvme_command *cmd, u32 *result, unsigned timeout)
|
|
{
|
|
int cmdid;
|
|
struct sync_cmd_info cmdinfo;
|
|
|
|
cmdinfo.task = current;
|
|
cmdinfo.status = -EINTR;
|
|
|
|
cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
|
|
timeout);
|
|
if (cmdid < 0)
|
|
return cmdid;
|
|
cmd->common.command_id = cmdid;
|
|
|
|
set_current_state(TASK_KILLABLE);
|
|
nvme_submit_cmd(nvmeq, cmd);
|
|
schedule();
|
|
|
|
if (cmdinfo.status == -EINTR) {
|
|
nvme_abort_command(nvmeq, cmdid);
|
|
return -EINTR;
|
|
}
|
|
|
|
if (result)
|
|
*result = cmdinfo.result;
|
|
|
|
return cmdinfo.status;
|
|
}
|
|
|
|
static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
|
|
u32 *result)
|
|
{
|
|
return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
|
|
}
|
|
|
|
static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
|
|
{
|
|
int status;
|
|
struct nvme_command c;
|
|
|
|
memset(&c, 0, sizeof(c));
|
|
c.delete_queue.opcode = opcode;
|
|
c.delete_queue.qid = cpu_to_le16(id);
|
|
|
|
status = nvme_submit_admin_cmd(dev, &c, NULL);
|
|
if (status)
|
|
return -EIO;
|
|
return 0;
|
|
}
|
|
|
|
static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
|
|
struct nvme_queue *nvmeq)
|
|
{
|
|
int status;
|
|
struct nvme_command c;
|
|
int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
|
|
|
|
memset(&c, 0, sizeof(c));
|
|
c.create_cq.opcode = nvme_admin_create_cq;
|
|
c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
|
|
c.create_cq.cqid = cpu_to_le16(qid);
|
|
c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
|
|
c.create_cq.cq_flags = cpu_to_le16(flags);
|
|
c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
|
|
|
|
status = nvme_submit_admin_cmd(dev, &c, NULL);
|
|
if (status)
|
|
return -EIO;
|
|
return 0;
|
|
}
|
|
|
|
static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
|
|
struct nvme_queue *nvmeq)
|
|
{
|
|
int status;
|
|
struct nvme_command c;
|
|
int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
|
|
|
|
memset(&c, 0, sizeof(c));
|
|
c.create_sq.opcode = nvme_admin_create_sq;
|
|
c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
|
|
c.create_sq.sqid = cpu_to_le16(qid);
|
|
c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
|
|
c.create_sq.sq_flags = cpu_to_le16(flags);
|
|
c.create_sq.cqid = cpu_to_le16(qid);
|
|
|
|
status = nvme_submit_admin_cmd(dev, &c, NULL);
|
|
if (status)
|
|
return -EIO;
|
|
return 0;
|
|
}
|
|
|
|
static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
|
|
{
|
|
return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
|
|
}
|
|
|
|
static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
|
|
{
|
|
return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
|
|
}
|
|
|
|
static void nvme_free_queue(struct nvme_dev *dev, int qid)
|
|
{
|
|
struct nvme_queue *nvmeq = dev->queues[qid];
|
|
|
|
free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
|
|
|
|
/* Don't tell the adapter to delete the admin queue */
|
|
if (qid) {
|
|
adapter_delete_sq(dev, qid);
|
|
adapter_delete_cq(dev, qid);
|
|
}
|
|
|
|
dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
|
|
(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
|
|
dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
|
|
nvmeq->sq_cmds, nvmeq->sq_dma_addr);
|
|
kfree(nvmeq);
|
|
}
|
|
|
|
static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
|
|
int depth, int vector)
|
|
{
|
|
struct device *dmadev = &dev->pci_dev->dev;
|
|
unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
|
|
struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
|
|
if (!nvmeq)
|
|
return NULL;
|
|
|
|
nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
|
|
&nvmeq->cq_dma_addr, GFP_KERNEL);
|
|
if (!nvmeq->cqes)
|
|
goto free_nvmeq;
|
|
memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
|
|
|
|
nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
|
|
&nvmeq->sq_dma_addr, GFP_KERNEL);
|
|
if (!nvmeq->sq_cmds)
|
|
goto free_cqdma;
|
|
|
|
nvmeq->q_dmadev = dmadev;
|
|
nvmeq->dev = dev;
|
|
spin_lock_init(&nvmeq->q_lock);
|
|
nvmeq->cq_head = 0;
|
|
nvmeq->cq_phase = 1;
|
|
init_waitqueue_head(&nvmeq->sq_full);
|
|
init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
|
|
bio_list_init(&nvmeq->sq_cong);
|
|
nvmeq->q_db = &dev->dbs[qid * 2];
|
|
nvmeq->q_depth = depth;
|
|
nvmeq->cq_vector = vector;
|
|
|
|
return nvmeq;
|
|
|
|
free_cqdma:
|
|
dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
|
|
nvmeq->cq_dma_addr);
|
|
free_nvmeq:
|
|
kfree(nvmeq);
|
|
return NULL;
|
|
}
|
|
|
|
static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
|
|
const char *name)
|
|
{
|
|
if (use_threaded_interrupts)
|
|
return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
|
|
nvme_irq_check, nvme_irq,
|
|
IRQF_DISABLED | IRQF_SHARED,
|
|
name, nvmeq);
|
|
return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
|
|
IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
|
|
}
|
|
|
|
static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
|
|
int qid, int cq_size, int vector)
|
|
{
|
|
int result;
|
|
struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
|
|
|
|
if (!nvmeq)
|
|
return NULL;
|
|
|
|
result = adapter_alloc_cq(dev, qid, nvmeq);
|
|
if (result < 0)
|
|
goto free_nvmeq;
|
|
|
|
result = adapter_alloc_sq(dev, qid, nvmeq);
|
|
if (result < 0)
|
|
goto release_cq;
|
|
|
|
result = queue_request_irq(dev, nvmeq, "nvme");
|
|
if (result < 0)
|
|
goto release_sq;
|
|
|
|
return nvmeq;
|
|
|
|
release_sq:
|
|
adapter_delete_sq(dev, qid);
|
|
release_cq:
|
|
adapter_delete_cq(dev, qid);
|
|
free_nvmeq:
|
|
dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
|
|
(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
|
|
dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
|
|
nvmeq->sq_cmds, nvmeq->sq_dma_addr);
|
|
kfree(nvmeq);
|
|
return NULL;
|
|
}
|
|
|
|
static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
|
|
{
|
|
int result;
|
|
u32 aqa;
|
|
struct nvme_queue *nvmeq;
|
|
|
|
dev->dbs = ((void __iomem *)dev->bar) + 4096;
|
|
|
|
nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
|
|
if (!nvmeq)
|
|
return -ENOMEM;
|
|
|
|
aqa = nvmeq->q_depth - 1;
|
|
aqa |= aqa << 16;
|
|
|
|
dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
|
|
dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
|
|
dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
|
|
|
|
writel(0, &dev->bar->cc);
|
|
writel(aqa, &dev->bar->aqa);
|
|
writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
|
|
writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
|
|
writel(dev->ctrl_config, &dev->bar->cc);
|
|
|
|
while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
|
|
msleep(100);
|
|
if (fatal_signal_pending(current))
|
|
return -EINTR;
|
|
}
|
|
|
|
result = queue_request_irq(dev, nvmeq, "nvme admin");
|
|
dev->queues[0] = nvmeq;
|
|
return result;
|
|
}
|
|
|
|
static int nvme_map_user_pages(struct nvme_dev *dev, int write,
|
|
unsigned long addr, unsigned length,
|
|
struct scatterlist **sgp)
|
|
{
|
|
int i, err, count, nents, offset;
|
|
struct scatterlist *sg;
|
|
struct page **pages;
|
|
|
|
if (addr & 3)
|
|
return -EINVAL;
|
|
if (!length)
|
|
return -EINVAL;
|
|
|
|
offset = offset_in_page(addr);
|
|
count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
|
|
pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
|
|
|
|
err = get_user_pages_fast(addr, count, 1, pages);
|
|
if (err < count) {
|
|
count = err;
|
|
err = -EFAULT;
|
|
goto put_pages;
|
|
}
|
|
|
|
sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
|
|
sg_init_table(sg, count);
|
|
sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
|
|
length -= (PAGE_SIZE - offset);
|
|
for (i = 1; i < count; i++) {
|
|
sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
|
|
length -= PAGE_SIZE;
|
|
}
|
|
|
|
err = -ENOMEM;
|
|
nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
|
|
write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
|
|
if (!nents)
|
|
goto put_pages;
|
|
|
|
kfree(pages);
|
|
*sgp = sg;
|
|
return nents;
|
|
|
|
put_pages:
|
|
for (i = 0; i < count; i++)
|
|
put_page(pages[i]);
|
|
kfree(pages);
|
|
return err;
|
|
}
|
|
|
|
static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
|
|
unsigned long addr, int length,
|
|
struct scatterlist *sg, int nents)
|
|
{
|
|
int i, count;
|
|
|
|
count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
|
|
dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
|
|
|
|
for (i = 0; i < count; i++)
|
|
put_page(sg_page(&sg[i]));
|
|
}
|
|
|
|
static int nvme_submit_user_admin_command(struct nvme_dev *dev,
|
|
unsigned long addr, unsigned length,
|
|
struct nvme_command *cmd)
|
|
{
|
|
int err, nents;
|
|
struct scatterlist *sg;
|
|
struct nvme_prps *prps;
|
|
|
|
nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
|
|
if (nents < 0)
|
|
return nents;
|
|
prps = nvme_setup_prps(dev, &cmd->common, sg, length);
|
|
err = nvme_submit_admin_cmd(dev, cmd, NULL);
|
|
nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
|
|
nvme_free_prps(dev, prps);
|
|
return err ? -EIO : 0;
|
|
}
|
|
|
|
static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
|
|
{
|
|
struct nvme_command c;
|
|
|
|
memset(&c, 0, sizeof(c));
|
|
c.identify.opcode = nvme_admin_identify;
|
|
c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
|
|
c.identify.cns = cpu_to_le32(cns);
|
|
|
|
return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
|
|
}
|
|
|
|
static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
|
|
{
|
|
struct nvme_command c;
|
|
|
|
memset(&c, 0, sizeof(c));
|
|
c.features.opcode = nvme_admin_get_features;
|
|
c.features.nsid = cpu_to_le32(ns->ns_id);
|
|
c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
|
|
|
|
return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
|
|
}
|
|
|
|
static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
|
|
{
|
|
struct nvme_dev *dev = ns->dev;
|
|
struct nvme_queue *nvmeq;
|
|
struct nvme_user_io io;
|
|
struct nvme_command c;
|
|
unsigned length;
|
|
u32 result;
|
|
int nents, status;
|
|
struct scatterlist *sg;
|
|
struct nvme_prps *prps;
|
|
|
|
if (copy_from_user(&io, uio, sizeof(io)))
|
|
return -EFAULT;
|
|
length = io.nblocks << io.block_shift;
|
|
nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
|
|
if (nents < 0)
|
|
return nents;
|
|
|
|
memset(&c, 0, sizeof(c));
|
|
c.rw.opcode = io.opcode;
|
|
c.rw.flags = io.flags;
|
|
c.rw.nsid = cpu_to_le32(io.nsid);
|
|
c.rw.slba = cpu_to_le64(io.slba);
|
|
c.rw.length = cpu_to_le16(io.nblocks - 1);
|
|
c.rw.control = cpu_to_le16(io.control);
|
|
c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
|
|
c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */
|
|
c.rw.apptag = cpu_to_le16(io.apptag);
|
|
c.rw.appmask = cpu_to_le16(io.appmask);
|
|
/* XXX: metadata */
|
|
prps = nvme_setup_prps(dev, &c.common, sg, length);
|
|
|
|
nvmeq = get_nvmeq(ns);
|
|
/* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
|
|
* disabled. We may be preempted at any point, and be rescheduled
|
|
* to a different CPU. That will cause cacheline bouncing, but no
|
|
* additional races since q_lock already protects against other CPUs.
|
|
*/
|
|
put_nvmeq(nvmeq);
|
|
status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
|
|
|
|
nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
|
|
nvme_free_prps(dev, prps);
|
|
put_user(result, &uio->result);
|
|
return status;
|
|
}
|
|
|
|
static int nvme_download_firmware(struct nvme_ns *ns,
|
|
struct nvme_dlfw __user *udlfw)
|
|
{
|
|
struct nvme_dev *dev = ns->dev;
|
|
struct nvme_dlfw dlfw;
|
|
struct nvme_command c;
|
|
int nents, status;
|
|
struct scatterlist *sg;
|
|
struct nvme_prps *prps;
|
|
|
|
if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
|
|
return -EFAULT;
|
|
if (dlfw.length >= (1 << 30))
|
|
return -EINVAL;
|
|
|
|
nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
|
|
if (nents < 0)
|
|
return nents;
|
|
|
|
memset(&c, 0, sizeof(c));
|
|
c.dlfw.opcode = nvme_admin_download_fw;
|
|
c.dlfw.numd = cpu_to_le32(dlfw.length);
|
|
c.dlfw.offset = cpu_to_le32(dlfw.offset);
|
|
prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
|
|
|
|
status = nvme_submit_admin_cmd(dev, &c, NULL);
|
|
nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
|
|
nvme_free_prps(dev, prps);
|
|
return status;
|
|
}
|
|
|
|
static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
|
|
{
|
|
struct nvme_dev *dev = ns->dev;
|
|
struct nvme_command c;
|
|
|
|
memset(&c, 0, sizeof(c));
|
|
c.common.opcode = nvme_admin_activate_fw;
|
|
c.common.rsvd10[0] = cpu_to_le32(arg);
|
|
|
|
return nvme_submit_admin_cmd(dev, &c, NULL);
|
|
}
|
|
|
|
static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
struct nvme_ns *ns = bdev->bd_disk->private_data;
|
|
|
|
switch (cmd) {
|
|
case NVME_IOCTL_IDENTIFY_NS:
|
|
return nvme_identify(ns, arg, 0);
|
|
case NVME_IOCTL_IDENTIFY_CTRL:
|
|
return nvme_identify(ns, arg, 1);
|
|
case NVME_IOCTL_GET_RANGE_TYPE:
|
|
return nvme_get_range_type(ns, arg);
|
|
case NVME_IOCTL_SUBMIT_IO:
|
|
return nvme_submit_io(ns, (void __user *)arg);
|
|
case NVME_IOCTL_DOWNLOAD_FW:
|
|
return nvme_download_firmware(ns, (void __user *)arg);
|
|
case NVME_IOCTL_ACTIVATE_FW:
|
|
return nvme_activate_firmware(ns, arg);
|
|
default:
|
|
return -ENOTTY;
|
|
}
|
|
}
|
|
|
|
static const struct block_device_operations nvme_fops = {
|
|
.owner = THIS_MODULE,
|
|
.ioctl = nvme_ioctl,
|
|
};
|
|
|
|
static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
|
|
{
|
|
while (bio_list_peek(&nvmeq->sq_cong)) {
|
|
struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
|
|
struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
|
|
if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
|
|
bio_list_add_head(&nvmeq->sq_cong, bio);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int nvme_kthread(void *data)
|
|
{
|
|
struct nvme_dev *dev;
|
|
|
|
while (!kthread_should_stop()) {
|
|
__set_current_state(TASK_RUNNING);
|
|
spin_lock(&dev_list_lock);
|
|
list_for_each_entry(dev, &dev_list, node) {
|
|
int i;
|
|
for (i = 0; i < dev->queue_count; i++) {
|
|
struct nvme_queue *nvmeq = dev->queues[i];
|
|
spin_lock_irq(&nvmeq->q_lock);
|
|
if (nvme_process_cq(nvmeq))
|
|
printk("process_cq did something\n");
|
|
nvme_resubmit_bios(nvmeq);
|
|
spin_unlock_irq(&nvmeq->q_lock);
|
|
}
|
|
}
|
|
spin_unlock(&dev_list_lock);
|
|
set_current_state(TASK_INTERRUPTIBLE);
|
|
schedule_timeout(HZ);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
|
|
struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
|
|
{
|
|
struct nvme_ns *ns;
|
|
struct gendisk *disk;
|
|
int lbaf;
|
|
|
|
if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
|
|
return NULL;
|
|
|
|
ns = kzalloc(sizeof(*ns), GFP_KERNEL);
|
|
if (!ns)
|
|
return NULL;
|
|
ns->queue = blk_alloc_queue(GFP_KERNEL);
|
|
if (!ns->queue)
|
|
goto out_free_ns;
|
|
ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
|
|
QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
|
|
blk_queue_make_request(ns->queue, nvme_make_request);
|
|
ns->dev = dev;
|
|
ns->queue->queuedata = ns;
|
|
|
|
disk = alloc_disk(NVME_MINORS);
|
|
if (!disk)
|
|
goto out_free_queue;
|
|
ns->ns_id = index;
|
|
ns->disk = disk;
|
|
lbaf = id->flbas & 0xf;
|
|
ns->lba_shift = id->lbaf[lbaf].ds;
|
|
|
|
disk->major = nvme_major;
|
|
disk->minors = NVME_MINORS;
|
|
disk->first_minor = NVME_MINORS * index;
|
|
disk->fops = &nvme_fops;
|
|
disk->private_data = ns;
|
|
disk->queue = ns->queue;
|
|
disk->driverfs_dev = &dev->pci_dev->dev;
|
|
sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
|
|
set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
|
|
|
|
return ns;
|
|
|
|
out_free_queue:
|
|
blk_cleanup_queue(ns->queue);
|
|
out_free_ns:
|
|
kfree(ns);
|
|
return NULL;
|
|
}
|
|
|
|
static void nvme_ns_free(struct nvme_ns *ns)
|
|
{
|
|
put_disk(ns->disk);
|
|
blk_cleanup_queue(ns->queue);
|
|
kfree(ns);
|
|
}
|
|
|
|
static int set_queue_count(struct nvme_dev *dev, int count)
|
|
{
|
|
int status;
|
|
u32 result;
|
|
struct nvme_command c;
|
|
u32 q_count = (count - 1) | ((count - 1) << 16);
|
|
|
|
memset(&c, 0, sizeof(c));
|
|
c.features.opcode = nvme_admin_get_features;
|
|
c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
|
|
c.features.dword11 = cpu_to_le32(q_count);
|
|
|
|
status = nvme_submit_admin_cmd(dev, &c, &result);
|
|
if (status)
|
|
return -EIO;
|
|
return min(result & 0xffff, result >> 16) + 1;
|
|
}
|
|
|
|
static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
|
|
{
|
|
int result, cpu, i, nr_queues;
|
|
|
|
nr_queues = num_online_cpus();
|
|
result = set_queue_count(dev, nr_queues);
|
|
if (result < 0)
|
|
return result;
|
|
if (result < nr_queues)
|
|
nr_queues = result;
|
|
|
|
/* Deregister the admin queue's interrupt */
|
|
free_irq(dev->entry[0].vector, dev->queues[0]);
|
|
|
|
for (i = 0; i < nr_queues; i++)
|
|
dev->entry[i].entry = i;
|
|
for (;;) {
|
|
result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
|
|
if (result == 0) {
|
|
break;
|
|
} else if (result > 0) {
|
|
nr_queues = result;
|
|
continue;
|
|
} else {
|
|
nr_queues = 1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
result = queue_request_irq(dev, dev->queues[0], "nvme admin");
|
|
/* XXX: handle failure here */
|
|
|
|
cpu = cpumask_first(cpu_online_mask);
|
|
for (i = 0; i < nr_queues; i++) {
|
|
irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
|
|
cpu = cpumask_next(cpu, cpu_online_mask);
|
|
}
|
|
|
|
for (i = 0; i < nr_queues; i++) {
|
|
dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
|
|
NVME_Q_DEPTH, i);
|
|
if (!dev->queues[i + 1])
|
|
return -ENOMEM;
|
|
dev->queue_count++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void nvme_free_queues(struct nvme_dev *dev)
|
|
{
|
|
int i;
|
|
|
|
for (i = dev->queue_count - 1; i >= 0; i--)
|
|
nvme_free_queue(dev, i);
|
|
}
|
|
|
|
static int __devinit nvme_dev_add(struct nvme_dev *dev)
|
|
{
|
|
int res, nn, i;
|
|
struct nvme_ns *ns, *next;
|
|
struct nvme_id_ctrl *ctrl;
|
|
void *id;
|
|
dma_addr_t dma_addr;
|
|
struct nvme_command cid, crt;
|
|
|
|
res = nvme_setup_io_queues(dev);
|
|
if (res)
|
|
return res;
|
|
|
|
/* XXX: Switch to a SG list once prp2 works */
|
|
id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
|
|
GFP_KERNEL);
|
|
|
|
memset(&cid, 0, sizeof(cid));
|
|
cid.identify.opcode = nvme_admin_identify;
|
|
cid.identify.nsid = 0;
|
|
cid.identify.prp1 = cpu_to_le64(dma_addr);
|
|
cid.identify.cns = cpu_to_le32(1);
|
|
|
|
res = nvme_submit_admin_cmd(dev, &cid, NULL);
|
|
if (res) {
|
|
res = -EIO;
|
|
goto out_free;
|
|
}
|
|
|
|
ctrl = id;
|
|
nn = le32_to_cpup(&ctrl->nn);
|
|
memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
|
|
memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
|
|
memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
|
|
|
|
cid.identify.cns = 0;
|
|
memset(&crt, 0, sizeof(crt));
|
|
crt.features.opcode = nvme_admin_get_features;
|
|
crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
|
|
crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
|
|
|
|
for (i = 0; i < nn; i++) {
|
|
cid.identify.nsid = cpu_to_le32(i);
|
|
res = nvme_submit_admin_cmd(dev, &cid, NULL);
|
|
if (res)
|
|
continue;
|
|
|
|
if (((struct nvme_id_ns *)id)->ncap == 0)
|
|
continue;
|
|
|
|
crt.features.nsid = cpu_to_le32(i);
|
|
res = nvme_submit_admin_cmd(dev, &crt, NULL);
|
|
if (res)
|
|
continue;
|
|
|
|
ns = nvme_alloc_ns(dev, i, id, id + 4096);
|
|
if (ns)
|
|
list_add_tail(&ns->list, &dev->namespaces);
|
|
}
|
|
list_for_each_entry(ns, &dev->namespaces, list)
|
|
add_disk(ns->disk);
|
|
|
|
dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
|
|
return 0;
|
|
|
|
out_free:
|
|
list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
|
|
list_del(&ns->list);
|
|
nvme_ns_free(ns);
|
|
}
|
|
|
|
dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
|
|
return res;
|
|
}
|
|
|
|
static int nvme_dev_remove(struct nvme_dev *dev)
|
|
{
|
|
struct nvme_ns *ns, *next;
|
|
|
|
spin_lock(&dev_list_lock);
|
|
list_del(&dev->node);
|
|
spin_unlock(&dev_list_lock);
|
|
|
|
/* TODO: wait all I/O finished or cancel them */
|
|
|
|
list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
|
|
list_del(&ns->list);
|
|
del_gendisk(ns->disk);
|
|
nvme_ns_free(ns);
|
|
}
|
|
|
|
nvme_free_queues(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nvme_setup_prp_pools(struct nvme_dev *dev)
|
|
{
|
|
struct device *dmadev = &dev->pci_dev->dev;
|
|
dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
|
|
PAGE_SIZE, PAGE_SIZE, 0);
|
|
if (!dev->prp_page_pool)
|
|
return -ENOMEM;
|
|
|
|
/* Optimisation for I/Os between 4k and 128k */
|
|
dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
|
|
256, 256, 0);
|
|
if (!dev->prp_small_pool) {
|
|
dma_pool_destroy(dev->prp_page_pool);
|
|
return -ENOMEM;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void nvme_release_prp_pools(struct nvme_dev *dev)
|
|
{
|
|
dma_pool_destroy(dev->prp_page_pool);
|
|
dma_pool_destroy(dev->prp_small_pool);
|
|
}
|
|
|
|
/* XXX: Use an ida or something to let remove / add work correctly */
|
|
static void nvme_set_instance(struct nvme_dev *dev)
|
|
{
|
|
static int instance;
|
|
dev->instance = instance++;
|
|
}
|
|
|
|
static void nvme_release_instance(struct nvme_dev *dev)
|
|
{
|
|
}
|
|
|
|
static int __devinit nvme_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *id)
|
|
{
|
|
int bars, result = -ENOMEM;
|
|
struct nvme_dev *dev;
|
|
|
|
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
|
|
GFP_KERNEL);
|
|
if (!dev->entry)
|
|
goto free;
|
|
dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
|
|
GFP_KERNEL);
|
|
if (!dev->queues)
|
|
goto free;
|
|
|
|
if (pci_enable_device_mem(pdev))
|
|
goto free;
|
|
pci_set_master(pdev);
|
|
bars = pci_select_bars(pdev, IORESOURCE_MEM);
|
|
if (pci_request_selected_regions(pdev, bars, "nvme"))
|
|
goto disable;
|
|
|
|
INIT_LIST_HEAD(&dev->namespaces);
|
|
dev->pci_dev = pdev;
|
|
pci_set_drvdata(pdev, dev);
|
|
dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
|
|
dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
|
|
nvme_set_instance(dev);
|
|
dev->entry[0].vector = pdev->irq;
|
|
|
|
result = nvme_setup_prp_pools(dev);
|
|
if (result)
|
|
goto disable_msix;
|
|
|
|
dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
|
|
if (!dev->bar) {
|
|
result = -ENOMEM;
|
|
goto disable_msix;
|
|
}
|
|
|
|
result = nvme_configure_admin_queue(dev);
|
|
if (result)
|
|
goto unmap;
|
|
dev->queue_count++;
|
|
|
|
result = nvme_dev_add(dev);
|
|
if (result)
|
|
goto delete;
|
|
|
|
spin_lock(&dev_list_lock);
|
|
list_add(&dev->node, &dev_list);
|
|
spin_unlock(&dev_list_lock);
|
|
|
|
return 0;
|
|
|
|
delete:
|
|
nvme_free_queues(dev);
|
|
unmap:
|
|
iounmap(dev->bar);
|
|
disable_msix:
|
|
pci_disable_msix(pdev);
|
|
nvme_release_instance(dev);
|
|
nvme_release_prp_pools(dev);
|
|
disable:
|
|
pci_disable_device(pdev);
|
|
pci_release_regions(pdev);
|
|
free:
|
|
kfree(dev->queues);
|
|
kfree(dev->entry);
|
|
kfree(dev);
|
|
return result;
|
|
}
|
|
|
|
static void __devexit nvme_remove(struct pci_dev *pdev)
|
|
{
|
|
struct nvme_dev *dev = pci_get_drvdata(pdev);
|
|
nvme_dev_remove(dev);
|
|
pci_disable_msix(pdev);
|
|
iounmap(dev->bar);
|
|
nvme_release_instance(dev);
|
|
nvme_release_prp_pools(dev);
|
|
pci_disable_device(pdev);
|
|
pci_release_regions(pdev);
|
|
kfree(dev->queues);
|
|
kfree(dev->entry);
|
|
kfree(dev);
|
|
}
|
|
|
|
/* These functions are yet to be implemented */
|
|
#define nvme_error_detected NULL
|
|
#define nvme_dump_registers NULL
|
|
#define nvme_link_reset NULL
|
|
#define nvme_slot_reset NULL
|
|
#define nvme_error_resume NULL
|
|
#define nvme_suspend NULL
|
|
#define nvme_resume NULL
|
|
|
|
static struct pci_error_handlers nvme_err_handler = {
|
|
.error_detected = nvme_error_detected,
|
|
.mmio_enabled = nvme_dump_registers,
|
|
.link_reset = nvme_link_reset,
|
|
.slot_reset = nvme_slot_reset,
|
|
.resume = nvme_error_resume,
|
|
};
|
|
|
|
/* Move to pci_ids.h later */
|
|
#define PCI_CLASS_STORAGE_EXPRESS 0x010802
|
|
|
|
static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
|
|
{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
|
|
{ 0, }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, nvme_id_table);
|
|
|
|
static struct pci_driver nvme_driver = {
|
|
.name = "nvme",
|
|
.id_table = nvme_id_table,
|
|
.probe = nvme_probe,
|
|
.remove = __devexit_p(nvme_remove),
|
|
.suspend = nvme_suspend,
|
|
.resume = nvme_resume,
|
|
.err_handler = &nvme_err_handler,
|
|
};
|
|
|
|
static int __init nvme_init(void)
|
|
{
|
|
int result = -EBUSY;
|
|
|
|
nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
|
|
if (IS_ERR(nvme_thread))
|
|
return PTR_ERR(nvme_thread);
|
|
|
|
nvme_major = register_blkdev(nvme_major, "nvme");
|
|
if (nvme_major <= 0)
|
|
goto kill_kthread;
|
|
|
|
result = pci_register_driver(&nvme_driver);
|
|
if (result)
|
|
goto unregister_blkdev;
|
|
return 0;
|
|
|
|
unregister_blkdev:
|
|
unregister_blkdev(nvme_major, "nvme");
|
|
kill_kthread:
|
|
kthread_stop(nvme_thread);
|
|
return result;
|
|
}
|
|
|
|
static void __exit nvme_exit(void)
|
|
{
|
|
pci_unregister_driver(&nvme_driver);
|
|
unregister_blkdev(nvme_major, "nvme");
|
|
kthread_stop(nvme_thread);
|
|
}
|
|
|
|
MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_VERSION("0.2");
|
|
module_init(nvme_init);
|
|
module_exit(nvme_exit);
|