87d0bab2cb
Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture. The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus. Some of configuration params could be passed from DT too if needed. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
11 lines
301 B
Text
11 lines
301 B
Text
NVIDIA Tegra AHB
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Required properties:
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- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb"
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- reg : Should contain 1 register ranges(address and length)
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Example:
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ahb: ahb@6000c004 {
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compatible = "nvidia,tegra20-ahb";
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reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
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};
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