f15cbe6f1a
This follows the sparc changes a439fe51a1.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/*
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* include/asm-sh/cpu-sh4/timer.h
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*
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* Copyright (C) 2004 Lineo Solutions, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_TIMER_H
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#define __ASM_CPU_SH4_TIMER_H
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/*
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* ---------------------------------------------------------------------------
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* TMU Common definitions for SH4 processors
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* SH7750S/SH7750R
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* SH7751/SH7751R
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* SH7760
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* SH-X3
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* ---------------------------------------------------------------------------
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*/
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#ifdef CONFIG_CPU_SUBTYPE_SHX3
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#define TMU_012_BASE 0xffc10000
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#define TMU_345_BASE 0xffc20000
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#else
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#define TMU_012_BASE 0xffd80000
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#define TMU_345_BASE 0xfe100000
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#endif
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#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
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#define TMU_012_TSTR (TMU_012_BASE + 0x04)
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#define TMU_345_TSTR (TMU_345_BASE + 0x04)
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#define TMU0_TCOR (TMU_012_BASE + 0x08)
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#define TMU0_TCNT (TMU_012_BASE + 0x0c)
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#define TMU0_TCR (TMU_012_BASE + 0x10)
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#define TMU1_TCOR (TMU_012_BASE + 0x14)
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#define TMU1_TCNT (TMU_012_BASE + 0x18)
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#define TMU1_TCR (TMU_012_BASE + 0x1c)
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#define TMU2_TCOR (TMU_012_BASE + 0x20)
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#define TMU2_TCNT (TMU_012_BASE + 0x24)
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#define TMU2_TCR (TMU_012_BASE + 0x28)
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#define TMU2_TCPR (TMU_012_BASE + 0x2c)
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#define TMU3_TCOR (TMU_345_BASE + 0x08)
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#define TMU3_TCNT (TMU_345_BASE + 0x0c)
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#define TMU3_TCR (TMU_345_BASE + 0x10)
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#define TMU4_TCOR (TMU_345_BASE + 0x14)
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#define TMU4_TCNT (TMU_345_BASE + 0x18)
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#define TMU4_TCR (TMU_345_BASE + 0x1c)
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#define TMU5_TCOR (TMU_345_BASE + 0x20)
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#define TMU5_TCNT (TMU_345_BASE + 0x24)
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#define TMU5_TCR (TMU_345_BASE + 0x28)
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#endif /* __ASM_CPU_SH4_TIMER_H */
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