774 lines
31 KiB
C
774 lines
31 KiB
C
/**************************************************************************
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*
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* Copyright © 2000-2008 Alacritech, Inc. All rights reserved.
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*
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* $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation
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* are those of the authors and should not be interpreted as representing
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* official policies, either expressed or implied, of Alacritech, Inc.
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*
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**************************************************************************/
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/*
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* FILENAME: sxg.h
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*
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* This is the base set of header definitions for the SXG driver.
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*/
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#ifndef __SXG_DRIVER_H__
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#define __SXG_DRIVER_H__
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#define p_net_device struct net_device *
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// SXG_STATS - Probably move these to someplace where
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// the slicstat (sxgstat?) program can get them.
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typedef struct _SXG_STATS {
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// Xmt
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u32 XmtNBL; // Offload send NBL count
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u64 DumbXmtBytes; // Dumbnic send bytes
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u64 SlowXmtBytes; // Slowpath send bytes
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u64 FastXmtBytes; // Fastpath send bytes
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u64 DumbXmtPkts; // Dumbnic send packets
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u64 SlowXmtPkts; // Slowpath send packets
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u64 FastXmtPkts; // Fastpath send packets
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u64 DumbXmtUcastPkts; // directed packets
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u64 DumbXmtMcastPkts; // Multicast packets
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u64 DumbXmtBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV
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u64 DumbXmtUcastBytes; // OID_GEN_DIRECTED_BYTES_XMIT
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u64 DumbXmtMcastBytes; // OID_GEN_MULTICAST_BYTES_XMIT
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u64 DumbXmtBcastBytes; // OID_GEN_BROADCAST_BYTES_XMIT
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u64 XmtErrors; // OID_GEN_XMIT_ERROR
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u64 XmtDiscards; // OID_GEN_XMIT_DISCARDS
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u64 XmtOk; // OID_GEN_XMIT_OK
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u64 XmtQLen; // OID_GEN_TRANSMIT_QUEUE_LENGTH
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u64 XmtZeroFull; // Transmit ring zero full
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// Rcv
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u32 RcvNBL; // Offload recieve NBL count
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u64 DumbRcvBytes; // dumbnic recv bytes
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u64 DumbRcvUcastBytes; // OID_GEN_DIRECTED_BYTES_RCV
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u64 DumbRcvMcastBytes; // OID_GEN_MULTICAST_BYTES_RCV
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u64 DumbRcvBcastBytes; // OID_GEN_BROADCAST_BYTES_RCV
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u64 SlowRcvBytes; // Slowpath recv bytes
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u64 FastRcvBytes; // Fastpath recv bytes
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u64 DumbRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV
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u64 DumbRcvTcpPkts; // See SxgCollectStats
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u64 DumbRcvUcastPkts; // directed packets
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u64 DumbRcvMcastPkts; // Multicast packets
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u64 DumbRcvBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV
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u64 SlowRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV
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u64 RcvErrors; // OID_GEN_RCV_ERROR
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u64 RcvDiscards; // OID_GEN_RCV_DISCARDS
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u64 RcvNoBuffer; // OID_GEN_RCV_NO_BUFFER
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u64 PdqFull; // Processed Data Queue Full
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u64 EventRingFull; // Event ring full
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// Verbose stats
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u64 MaxSends; // Max sends outstanding
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u64 NoSglBuf; // SGL buffer allocation failure
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u64 SglFail; // NDIS SGL failure
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u64 SglAsync; // NDIS SGL failure
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u64 NoMem; // Memory allocation failure
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u64 NumInts; // Interrupts
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u64 FalseInts; // Interrupt with ISR == 0
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u64 XmtDrops; // No sahara DRAM buffer for xmt
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// Sahara receive status
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u64 TransportCsum; // SXG_RCV_STATUS_TRANSPORT_CSUM
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u64 TransportUflow; // SXG_RCV_STATUS_TRANSPORT_UFLOW
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u64 TransportHdrLen; // SXG_RCV_STATUS_TRANSPORT_HDRLEN
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u64 NetworkCsum; // SXG_RCV_STATUS_NETWORK_CSUM:
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u64 NetworkUflow; // SXG_RCV_STATUS_NETWORK_UFLOW:
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u64 NetworkHdrLen; // SXG_RCV_STATUS_NETWORK_HDRLEN:
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u64 Parity; // SXG_RCV_STATUS_PARITY
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u64 LinkParity; // SXG_RCV_STATUS_LINK_PARITY:
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u64 LinkEarly; // SXG_RCV_STATUS_LINK_EARLY:
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u64 LinkBufOflow; // SXG_RCV_STATUS_LINK_BUFOFLOW:
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u64 LinkCode; // SXG_RCV_STATUS_LINK_CODE:
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u64 LinkDribble; // SXG_RCV_STATUS_LINK_DRIBBLE:
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u64 LinkCrc; // SXG_RCV_STATUS_LINK_CRC:
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u64 LinkOflow; // SXG_RCV_STATUS_LINK_OFLOW:
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u64 LinkUflow; // SXG_RCV_STATUS_LINK_UFLOW:
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} SXG_STATS, *PSXG_STATS;
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/****************************************************************************
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* DUMB-NIC Send path definitions
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****************************************************************************/
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#define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb) { \
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ASSERT(_skb); \
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dev_kfree_skb_irq(_skb); \
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}
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#define SXG_DROP_DUMB_SEND(_pAdapt, _skb) { \
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ASSERT(_skb); \
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dev_kfree_skb(_skb); \
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}
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// Locate current receive header buffer location. Use this
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// instead of RcvDataHdr->VirtualAddress since the data
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// may have been offset by SXG_ADVANCE_MDL_OFFSET
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#define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data
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/************************************************************************
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* Dumb-NIC receive processing
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************************************************************************/
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// Define an SXG_PACKET as an NDIS_PACKET
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#define PSXG_PACKET struct sk_buff *
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// Indications array size
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#define SXG_RCV_ARRAYSIZE 64
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#define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr) { \
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struct sk_buff * skb; \
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skb = alloc_skb(2048, GFP_ATOMIC); \
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if (skb) { \
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(_RcvDataBufferHdr)->skb = skb; \
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skb->next = NULL; \
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} else { \
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(_RcvDataBufferHdr)->skb = NULL; \
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} \
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}
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#define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) { \
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if((_RcvDataBufferHdr)->skb) { \
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dev_kfree_skb((_RcvDataBufferHdr)->skb); \
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} \
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}
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// Macro to add a NDIS_PACKET to an indication array
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// If we fill up our array of packet pointers, then indicate this
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// block up now and start on a new one.
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#define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, _NumPackets) { \
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(_IndicationList)[_NumPackets] = (_Packet); \
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(_NumPackets)++; \
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if((_NumPackets) == SXG_RCV_ARRAYSIZE) { \
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
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(_NumPackets), 0, 0, 0); \
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netif_rx((_IndicationList),(_NumPackets)); \
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(_NumPackets) = 0; \
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} \
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}
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#define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) { \
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if(_NumPackets) { \
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
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(_NumPackets), 0, 0, 0); \
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netif_rx((_IndicationList),(_NumPackets)); \
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(_NumPackets) = 0; \
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} \
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}
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#define SXG_REINIATIALIZE_PACKET(_Packet) \
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{} /*_NdisReinitializePacket(_Packet)*/ /* this is not necessary with an skb */
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// Definitions to initialize Dumb-nic Receive NBLs
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#define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((PSXG_RCV_NBL_RESERVED)((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
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#define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \
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NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
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#define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) { \
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NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz)); \
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NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type)); \
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NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function)); \
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}
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#define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) { \
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NDIS_PACKET_8021Q_INFO _Packet8021qInfo; \
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_Packet8021qInfo.TagHeader.VlanId = (_VlanId); \
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_Packet8021qInfo.TagHeader.UserPriority = (_Priority); \
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NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) = \
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_Packet8021qInfo.Value; \
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}
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#define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) { \
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv", \
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(_RcvDataBufferHdr), (_Packet), \
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(_Event)->Status, 0); \
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ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size); \
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Packet->len = (_Event)->Length; \
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}
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///////////////////////////////////////////////////////////////////////////////
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// Macros to free a receive data buffer and receive data descriptor block
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///////////////////////////////////////////////////////////////////////////////
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// NOTE - Lock must be held with RCV macros
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#define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
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PLIST_ENTRY _ple; \
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_Hdr = NULL; \
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if((_pAdapt)->FreeRcvBufferCount) { \
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ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \
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_ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \
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(_Hdr) = container_of(_ple, SXG_RCV_DATA_BUFFER_HDR, FreeList); \
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(_pAdapt)->FreeRcvBufferCount--; \
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ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \
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} \
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}
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#define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr", \
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(_Hdr), (_pAdapt)->FreeRcvBufferCount, \
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(_Hdr)->State, (_Hdr)->VirtualAddress); \
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/* SXG_RESTORE_MDL_OFFSET(_Hdr); */ \
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(_pAdapt)->FreeRcvBufferCount++; \
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ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) >= (_pAdapt)->FreeRcvBufferCount); \
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ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
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(_Hdr)->State = SXG_BUFFER_FREE; \
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InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList)); \
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}
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#define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) { \
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ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
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(_Hdr)->State = SXG_BUFFER_FREE; \
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(_pAdapt)->FreeRcvBlockCount++; \
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ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount); \
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InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \
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}
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// SGL macros
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#define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) { \
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spin_lock(&(_pAdapt)->SglQLock); \
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(_pAdapt)->FreeSglBufferCount++; \
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ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount);\
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ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE)); \
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(_Sgl)->State = SXG_BUFFER_FREE; \
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InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList); \
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spin_unlock(&(_pAdapt)->SglQLock); \
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}
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// Get an SGL buffer from the free queue. The first part of this macro
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// attempts to keep ahead of buffer depletion by allocating more when
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// we hit a minimum threshold. Note that we don't grab the lock
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// until after that. We're dealing with round numbers here, so we don't need to,
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// and not grabbing it avoids a possible double-trip.
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#define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) { \
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PLIST_ENTRY _ple; \
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if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \
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(_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) && \
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(_pAdapt->AllocationsPending == 0)) { \
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sxg_allocate_buffer_memory(_pAdapt, \
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(sizeof(SXG_SCATTER_GATHER) + SXG_SGL_BUF_SIZE),\
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SXG_BUFFER_TYPE_SGL); \
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} \
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_Sgl = NULL; \
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spin_lock(&(_pAdapt)->SglQLock); \
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if((_pAdapt)->FreeSglBufferCount) { \
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ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \
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_ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \
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(_Sgl) = container_of(_ple, SXG_SCATTER_GATHER, FreeList); \
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(_pAdapt)->FreeSglBufferCount--; \
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ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \
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(_Sgl)->State = SXG_BUFFER_BUSY; \
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(_Sgl)->pSgl = NULL; \
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} \
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spin_unlock(&(_pAdapt)->SglQLock); \
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}
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//
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// SXG_MULTICAST_ADDRESS
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//
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// Linked list of multicast addresses.
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typedef struct _SXG_MULTICAST_ADDRESS {
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unsigned char Address[6];
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struct _SXG_MULTICAST_ADDRESS *Next;
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} SXG_MULTICAST_ADDRESS, *PSXG_MULTICAST_ADDRESS;
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// Structure to maintain chimney send and receive buffer queues.
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// This structure maintains NET_BUFFER_LIST queues that are
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// given to us via the Chimney MiniportTcpOffloadSend and
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// MiniportTcpOffloadReceive routines. This structure DOES NOT
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// manage our data buffer queue
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typedef struct _SXG_BUFFER_QUEUE {
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u32 Type; // Slow or fast - See below
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u32 Direction; // Xmt or Rcv
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u32 Bytes; // Byte count
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u32 * Head; // Send queue head
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u32 * Tail; // Send queue tail
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// PNET_BUFFER_LIST NextNBL; // Short cut - next NBL
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// PNET_BUFFER NextNB; // Short cut - next NB
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} SXG_BUFFER_QUEUE, *PSXG_BUFFER_QUEUE;
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#define SXG_SLOW_SEND_BUFFER 0
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#define SXG_FAST_SEND_BUFFER 1
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#define SXG_RECEIVE_BUFFER 2
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#define SXG_INIT_BUFFER(_Buffer, _Type) { \
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(_Buffer)->Type = (_Type); \
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if((_Type) == SXG_RECEIVE_BUFFER) { \
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(_Buffer)->Direction = 0; \
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} else { \
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(_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE; \
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} \
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(_Buffer)->Bytes = 0; \
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(_Buffer)->Head = NULL; \
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(_Buffer)->Tail = NULL; \
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}
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#define SXG_RSS_CPU_COUNT(_pAdapt) \
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((_pAdapt)->RssEnabled ? NR_CPUS : 1)
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/****************************************************************************
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* DRIVER and ADAPTER structures
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****************************************************************************/
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// Adapter states - These states closely match the adapter states
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// documented in the DDK (with a few exceptions).
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typedef enum _SXG_STATE {
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SXG_STATE_INITIALIZING, // Initializing
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SXG_STATE_BOOTDIAG, // Boot-Diagnostic mode
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SXG_STATE_PAUSING, // Pausing
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SXG_STATE_PAUSED, // Paused
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SXG_STATE_RUNNING, // Running
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SXG_STATE_RESETTING, // Reset in progress
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SXG_STATE_SLEEP, // Sleeping
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SXG_STATE_DIAG, // Diagnostic mode
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SXG_STATE_HALTING, // Halting
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SXG_STATE_HALTED, // Down or not-initialized
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SXG_STATE_SHUTDOWN // shutdown
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} SXG_STATE, *PSXG_STATE;
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// Link state
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typedef enum _SXG_LINK_STATE {
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SXG_LINK_DOWN,
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SXG_LINK_UP
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} SXG_LINK_STATE, *PSXG_LINK_STATE;
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// Link initialization timeout in 100us units
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#define SXG_LINK_TIMEOUT 100000 // 10 Seconds - REDUCE!
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// Microcode file selection codes
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typedef enum _SXG_UCODE_SEL {
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SXG_UCODE_SAHARA, // Sahara ucode
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SXG_UCODE_SDIAGCPU, // Sahara CPU diagnostic ucode
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SXG_UCODE_SDIAGSYS // Sahara system diagnostic ucode
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} SXG_UCODE_SEL;
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#define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
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#define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
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// This probably lives in a proto.h file. Move later
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#define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
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#define SXG_BROADCAST_PACKET(_pether) ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
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(*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
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// For DbgPrints
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#define SXG_ID DPFLTR_IHVNETWORK_ID
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#define SXG_ERROR DPFLTR_ERROR_LEVEL
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//
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// SXG_DRIVER structure -
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//
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// contains information about the sxg driver. There is only
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// one of these, and it is defined as a global.
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typedef struct _SXG_DRIVER {
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struct _adapter_t *Adapters; // Linked list of adapters
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ushort AdapterID; // Maintain unique adapter ID
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} SXG_DRIVER, *PSXG_DRIVER;
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#ifdef STATUS_SUCCESS
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#undef STATUS_SUCCESS
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#endif
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#define STATUS_SUCCESS 0
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#define STATUS_PENDING 0
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#define STATUS_FAILURE -1
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#define STATUS_ERROR -2
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#define STATUS_NOT_SUPPORTED -3
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#define STATUS_BUFFER_TOO_SHORT -4
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#define STATUS_RESOURCES -5
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#define SLIC_MAX_CARDS 32
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#define SLIC_MAX_PORTS 4 /* Max # of ports per card */
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#if SLIC_DUMP_ENABLED
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// Dump buffer size
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//
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// This cannot be bigger than the max DMA size the card supports,
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// given the current code structure in the host and ucode.
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// Mojave supports 16K, Oasis supports 16K-1, so
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// just set this at 15K, shouldnt make that much of a diff.
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#define DUMP_BUF_SIZE 0x3C00
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#endif
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#define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
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#define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
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typedef struct _mcast_address_t
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{
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unsigned char address[6];
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struct _mcast_address_t *next;
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} mcast_address_t, *p_mcast_address_t;
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#define CARD_DOWN 0x00000000
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#define CARD_UP 0x00000001
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#define CARD_FAIL 0x00000002
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#define CARD_DIAG 0x00000003
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#define CARD_SLEEP 0x00000004
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#define ADAPT_DOWN 0x00
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#define ADAPT_UP 0x01
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#define ADAPT_FAIL 0x02
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#define ADAPT_RESET 0x03
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#define ADAPT_SLEEP 0x04
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#define ADAPT_FLAGS_BOOTTIME 0x0001
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#define ADAPT_FLAGS_IS64BIT 0x0002
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#define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
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#define ADAPT_FLAGS_FIBERMEDIA 0x0008
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#define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
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#define ADAPT_FLAGS_INT_REGISTERED 0x0020
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#define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
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#define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
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#define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
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#define LINK_DOWN 0x00
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#define LINK_CONFIG 0x01
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#define LINK_UP 0x02
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#define LINK_10MB 0x00
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#define LINK_100MB 0x01
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#define LINK_AUTOSPEED 0x02
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#define LINK_1000MB 0x03
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#define LINK_10000MB 0x04
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#define LINK_HALFD 0x00
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#define LINK_FULLD 0x01
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#define LINK_AUTOD 0x02
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#define MAC_DIRECTED 0x00000001
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#define MAC_BCAST 0x00000002
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#define MAC_MCAST 0x00000004
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#define MAC_PROMISC 0x00000008
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#define MAC_LOOPBACK 0x00000010
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#define MAC_ALLMCAST 0x00000020
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#define SLIC_DUPLEX(x) ((x==LINK_FULLD) ? "FDX" : "HDX")
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#define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
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#define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up ")
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#define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
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#define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down")
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typedef struct _ether_header
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{
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unsigned char ether_dhost[6];
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unsigned char ether_shost[6];
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ushort ether_type;
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} ether_header, *p_ether_header;
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#define NUM_CFG_SPACES 2
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#define NUM_CFG_REGS 64
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typedef struct _physcard_t
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{
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struct _adapter_t *adapter[SLIC_MAX_PORTS];
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struct _physcard_t *next;
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unsigned int adapters_allocd;
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} physcard_t, *p_physcard_t;
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typedef struct _sxgbase_driver
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{
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spinlock_t driver_lock;
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unsigned long flags; /* irqsave for spinlock */
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u32 num_sxg_cards;
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u32 num_sxg_ports;
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u32 num_sxg_ports_active;
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u32 dynamic_intagg;
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p_physcard_t phys_card;
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} sxgbase_driver_t;
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typedef struct _adapter_t
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{
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void * ifp;
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unsigned int port;
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p_physcard_t physcard;
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unsigned int physport;
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unsigned int cardindex;
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unsigned int card_size;
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unsigned int chipid;
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unsigned int busnumber;
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unsigned int slotnumber;
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unsigned int functionnumber;
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ushort vendid;
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ushort devid;
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ushort subsysid;
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u32 irq;
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void * sxg_adapter;
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u32 nBusySend;
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void __iomem * base_addr;
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u32 memorylength;
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u32 drambase;
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u32 dramlength;
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unsigned int queues_initialized;
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unsigned int allocated;
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unsigned int activated;
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u32 intrregistered;
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unsigned int isp_initialized;
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unsigned int gennumber;
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u32 curaddrupper;
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u32 isrcopy;
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unsigned char state;
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unsigned char linkstate;
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unsigned char linkspeed;
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unsigned char linkduplex;
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unsigned int flags;
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unsigned char macaddr[6];
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unsigned char currmacaddr[6];
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u32 macopts;
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ushort devflags_prev;
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u64 mcastmask;
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p_mcast_address_t mcastaddrs;
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struct timer_list pingtimer;
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u32 pingtimerset;
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struct timer_list statstimer;
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u32 statstimerset;
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struct timer_list vpci_timer;
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u32 vpci_timerset;
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struct timer_list loadtimer;
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u32 loadtimerset;
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u32 xmitq_full;
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u32 all_reg_writes;
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u32 icr_reg_writes;
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u32 isr_reg_writes;
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u32 error_interrupts;
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u32 error_rmiss_interrupts;
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u32 rx_errors;
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u32 rcv_drops;
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u32 rcv_interrupts;
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u32 xmit_interrupts;
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u32 linkevent_interrupts;
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u32 upr_interrupts;
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u32 num_isrs;
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u32 false_interrupts;
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u32 tx_packets;
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u32 xmit_completes;
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u32 tx_drops;
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u32 rcv_broadcasts;
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u32 rcv_multicasts;
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u32 rcv_unicasts;
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u32 max_isr_rcvs;
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u32 max_isr_xmits;
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u32 rcv_interrupt_yields;
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u32 intagg_period;
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struct net_device_stats stats;
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u32 * MiniportHandle; // Our miniport handle
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SXG_STATE State; // Adapter state
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SXG_LINK_STATE LinkState; // Link state
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u64 LinkSpeed; // Link Speed
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u32 PowerState; // NDIS power state
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struct _adapter_t *Next; // Linked list
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ushort AdapterID; // 1..n
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unsigned char MacAddr[6]; // Our permanent HW mac address
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unsigned char CurrMacAddr[6]; // Our Current mac address
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p_net_device netdev;
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p_net_device next_netdevice;
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struct pci_dev * pcidev;
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PSXG_MULTICAST_ADDRESS MulticastAddrs; // Multicast list
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u64 MulticastMask; // Multicast mask
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u32 * InterruptHandle; // Register Interrupt handle
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u32 InterruptLevel; // From Resource list
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u32 InterruptVector; // From Resource list
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spinlock_t AdapterLock; /* Serialize access adapter routines */
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spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
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PSXG_HW_REGS HwRegs; // Sahara HW Register Memory (BAR0/1)
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PSXG_UCODE_REGS UcodeRegs; // Microcode Register Memory (BAR2/3)
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PSXG_TCB_REGS TcbRegs; // Same as Ucode regs - See sxghw.h
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ushort ResetDpcCount; // For timeout
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ushort RssDpcCount; // For timeout
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ushort VendorID; // Vendor ID
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ushort DeviceID; // Device ID
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ushort SubSystemID; // Sub-System ID
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ushort FrameSize; // Maximum frame size
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u32 * DmaHandle; // NDIS DMA handle
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u32 * PacketPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
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u32 * BufferPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
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u32 MacFilter; // NDIS MAC Filter
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ushort IpId; // For slowpath
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PSXG_EVENT_RING EventRings; // Host event rings. 1/CPU to 16 max
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dma_addr_t PEventRings; // Physical address
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u32 NextEvent[SXG_MAX_RSS]; // Current location in ring
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dma_addr_t PTcbBuffers; // TCB Buffers - physical address
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dma_addr_t PTcbCompBuffers; // TCB Composite Buffers - phys addr
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PSXG_XMT_RING XmtRings; // Transmit rings
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dma_addr_t PXmtRings; // Transmit rings - physical address
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SXG_RING_INFO XmtRingZeroInfo; // Transmit ring 0 info
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spinlock_t XmtZeroLock; /* Transmit ring 0 lock */
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u32 * XmtRingZeroIndex; // Shared XMT ring 0 index
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dma_addr_t PXmtRingZeroIndex; // Shared XMT ring 0 index - physical
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LIST_ENTRY FreeProtocolHeaders;// Free protocol headers
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u32 FreeProtoHdrCount; // Count
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void * ProtocolHeaders; // Block of protocol header
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dma_addr_t PProtocolHeaders; // Block of protocol headers - phys
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PSXG_RCV_RING RcvRings; // Receive rings
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dma_addr_t PRcvRings; // Receive rings - physical address
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SXG_RING_INFO RcvRingZeroInfo; // Receive ring 0 info
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u32 * Isr; // Interrupt status register
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dma_addr_t PIsr; // ISR - physical address
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u32 IsrCopy[SXG_MAX_RSS]; // Copy of ISR
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ushort InterruptsEnabled; // Bitmask of enabled vectors
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unsigned char * IndirectionTable; // RSS indirection table
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dma_addr_t PIndirectionTable; // Physical address
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ushort RssTableSize; // From NDIS_RECEIVE_SCALE_PARAMETERS
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ushort HashKeySize; // From NDIS_RECEIVE_SCALE_PARAMETERS
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unsigned char HashSecretKey[40]; // rss key
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u32 HashInformation;
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// Receive buffer queues
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spinlock_t RcvQLock; /* Receive Queue Lock */
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LIST_ENTRY FreeRcvBuffers; // Free SXG_DATA_BUFFER queue
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LIST_ENTRY FreeRcvBlocks; // Free SXG_RCV_DESCRIPTOR_BLOCK Q
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LIST_ENTRY AllRcvBlocks; // All SXG_RCV_BLOCKs
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ushort FreeRcvBufferCount; // Number of free rcv data buffers
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ushort FreeRcvBlockCount; // # of free rcv descriptor blocks
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ushort AllRcvBlockCount; // Number of total receive blocks
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ushort ReceiveBufferSize; // SXG_RCV_DATA/JUMBO_BUFFER_SIZE only
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u32 AllocationsPending; // Receive allocation pending
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u32 RcvBuffersOnCard; // SXG_DATA_BUFFERS owned by card
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// SGL buffers
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spinlock_t SglQLock; /* SGL Queue Lock */
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LIST_ENTRY FreeSglBuffers; // Free SXG_SCATTER_GATHER
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LIST_ENTRY AllSglBuffers; // All SXG_SCATTER_GATHER
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ushort FreeSglBufferCount; // Number of free SGL buffers
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ushort AllSglBufferCount; // Number of total SGL buffers
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u32 CurrentTime; // Tick count
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u32 FastpathConnections;// # of fastpath connections
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// Various single-bit flags:
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u32 BasicAllocations:1; // Locks and listheads
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u32 IntRegistered:1; // Interrupt registered
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u32 PingOutstanding:1; // Ping outstanding to card
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u32 Dead:1; // Card dead
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u32 DumpDriver:1; // OID_SLIC_DRIVER_DUMP request
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u32 DumpCard:1; // OID_SLIC_CARD_DUMP request
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u32 DumpCmdRunning:1; // Dump command in progress
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u32 DebugRunning:1; // AGDB debug in progress
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u32 JumboEnabled:1; // Jumbo frames enabled
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u32 MsiEnabled:1; // MSI interrupt enabled
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u32 RssEnabled:1; // RSS Enabled
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u32 FailOnBadEeprom:1; // Fail on Bad Eeprom
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u32 DiagStart:1; // Init adapter for diagnostic start
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// Stats
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u32 PendingRcvCount; // Outstanding rcv indications
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u32 PendingXmtCount; // Outstanding send requests
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SXG_STATS Stats; // Statistics
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u32 ReassBufs; // Number of reassembly buffers
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// Card Crash Info
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ushort CrashLocation; // Microcode crash location
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unsigned char CrashCpu; // Sahara CPU ID
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// Diagnostics
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// PDIAG_CMD DiagCmds; // List of free diagnostic commands
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// PDIAG_BUFFER DiagBuffers; // List of free diagnostic buffers
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// PDIAG_REQ DiagReqQ; // List of outstanding (asynchronous) diag requests
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// u32 DiagCmdTimeout; // Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var?
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// unsigned char DiagDmaDesc[DMA_CPU_CTXS]; // Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx)
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/////////////////////////////////////////////////////////////////////
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// Put preprocessor-conditional fields at the end so we don't
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// have to recompile sxgdbg everytime we reconfigure the driver
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/////////////////////////////////////////////////////////////////////
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void * PendingSetRss; // Pending RSS parameter change
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u32 IPv4HdrSize; // Shared 5.2/6.0 encap param
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unsigned char * InterruptInfo; // Allocated by us during AddDevice
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#if defined(CONFIG_X86)
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u32 AddrUpper; // Upper 32 bits of 64-bit register
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#endif
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//#if SXG_FAILURE_DUMP
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// NDIS_EVENT DumpThreadEvent; // syncronize dump thread
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// BOOLEAN DumpThreadRunning; // termination flag
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// PSXG_DUMP_CMD DumpBuffer; // 68k - Cmd and Buffer
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// dma_addr_t PDumpBuffer; // Physical address
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//#endif // SXG_FAILURE_DUMP
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} adapter_t, *p_adapter_t;
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#if SLIC_DUMP_ENABLED
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#define SLIC_DUMP_REQUESTED 1
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#define SLIC_DUMP_IN_PROGRESS 2
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#define SLIC_DUMP_DONE 3
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/****************************************************************************
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*
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* Microcode crash information structure. This
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* structure is written out to the card's SRAM when the microcode panic's.
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*
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****************************************************************************/
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typedef struct _slic_crash_info {
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ushort cpu_id;
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ushort crash_pc;
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} slic_crash_info, *p_slic_crash_info;
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#define CRASH_INFO_OFFSET 0x155C
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#endif
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#define UPDATE_STATS(largestat, newstat, oldstat) \
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{ \
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if ((newstat) < (oldstat)) \
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(largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \
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else \
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(largestat) += ((newstat) - (oldstat)); \
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}
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#define UPDATE_STATS_GB(largestat, newstat, oldstat) \
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{ \
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(largestat) += ((newstat) - (oldstat)); \
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}
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#define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \
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{ \
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_Result = TRUE; \
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if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \
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_Result = FALSE; \
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if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \
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_Result = FALSE; \
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}
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#define ETHERMAXFRAME 1514
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#define JUMBOMAXFRAME 9014
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#if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
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#define SXG_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
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#define SXG_GET_ADDR_HIGH(_addr) (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
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#else
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#define SXG_GET_ADDR_LOW(_addr) (u32)_addr
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#define SXG_GET_ADDR_HIGH(_addr) (u32)0
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#endif
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#define FLUSH TRUE
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#define DONT_FLUSH FALSE
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#define SIOCSLICDUMPCARD SIOCDEVPRIVATE+9
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#define SIOCSLICSETINTAGG SIOCDEVPRIVATE+10
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#define SIOCSLICTRACEDUMP SIOCDEVPRIVATE+11
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#endif /* __SXG_DRIVER_H__ */
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