320de7d01c
If we make all MCF_RCR (CPU reset register) addressing consistent across all ColdFire CPU family members that use it then we will be able to remove the duplicated copies of the code that use it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
203 lines
7 KiB
C
203 lines
7 KiB
C
/****************************************************************************/
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/*
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* m523xsim.h -- ColdFire 523x System Integration Module support.
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*
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* (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
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*/
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/****************************************************************************/
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#ifndef m523xsim_h
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#define m523xsim_h
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/****************************************************************************/
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#define CPU_NAME "COLDFIRE(m523x)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK (MCF_CLK / 2)
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#include <asm/m52xxacr.h>
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/*
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* Define the 523x SIM register set addresses.
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*/
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#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
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#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_IRLR 0x18 /* */
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#define MCFINTC_IACKL 0x19 /* */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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#define MCFINT_VECBASE 64 /* Vector base number */
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#define MCFINT_UART0 13 /* Interrupt number for UART0 */
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#define MCFINT_UART1 14 /* Interrupt number for UART1 */
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#define MCFINT_UART2 15 /* Interrupt number for UART2 */
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#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
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#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
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#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
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#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
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#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
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#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
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#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
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#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
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#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
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#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
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#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
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#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
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/*
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* SDRAM configuration registers.
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*/
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#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
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#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
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#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
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#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
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#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
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/*
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* Reset Control Unit (relative to IPSBAR).
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*/
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#define MCF_RCR (MCF_IPSBAR + 0x110000)
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#define MCF_RSR (MCF_IPSBAR + 0x110001)
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#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
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#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
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/*
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* UART module.
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*/
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#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
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#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
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#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
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/*
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* FEC ethernet module.
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*/
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#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
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#define MCFFEC_SIZE0 0x800
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/*
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* QSPI module.
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*/
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#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
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#define MCFQSPI_SIZE 0x40
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#define MCFQSPI_CS0 91
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#define MCFQSPI_CS1 92
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#define MCFQSPI_CS2 103
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#define MCFQSPI_CS3 99
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/*
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* GPIO module.
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*/
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#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
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#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
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#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
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#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
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#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
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#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
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#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
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#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
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#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
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#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
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#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
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#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
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#define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
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#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
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#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
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#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
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#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
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#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
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#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
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#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
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#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
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#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
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#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
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#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
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#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
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#define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
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#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
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#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
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#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
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#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
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#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
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#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
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#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
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#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
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#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
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#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
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#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
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#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
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#define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
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#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
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#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
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#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
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#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
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#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
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#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
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#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
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#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
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#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
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#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
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#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
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#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
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#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
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/*
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* PIT timer base addresses.
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*/
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#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
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#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
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#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
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#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
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/*
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* EPort
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*/
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#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
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#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
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#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
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#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
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#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
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#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
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#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
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#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
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#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
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#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
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#define MCFGPIO_PIN_MAX 107
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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/*
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* Pin Assignment
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*/
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#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
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#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
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/*
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* DMA unit base addresses.
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*/
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#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
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#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
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#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
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#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
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/****************************************************************************/
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#endif /* m523xsim_h */
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