1fb3726cf3
The timer irqs statically mapped from linux irq numbers 11 to 15 are moved to the end of the statically mapped linux irq space. The GIC PPI and SPI interrupts are relocated to start from 16 and 32 of the linux irq space. This is a required to add device tree support for GIC and Interrupt combiner for EXYNOS4. A new macro 'IRQ_TIMER_BASE' specifies a platform specific base of the linux virq number for the timer interrupts. For exynos4, this base is set to end of the linux virq space. For the other S5P platforms, the existing base '11' is retained. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
150 lines
5 KiB
C
150 lines
5 KiB
C
/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
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*
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* Copyright 2009-2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5P64X0 - IRQ definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H __FILE__
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#include <plat/irqs.h>
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/* VIC0 */
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#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
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#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
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#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
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#define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */
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#define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */
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#define IRQ_IIC1 S5P_IRQ_VIC0(5)
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#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
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#define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */
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#define IRQ_2D S5P_IRQ_VIC0(11)
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#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
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#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
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#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25)
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#define IRQ_WDT S5P_IRQ_VIC0(26)
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#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27)
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#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28)
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#define IRQ_DISPCON0 S5P_IRQ_VIC0(29)
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#define IRQ_DISPCON1 S5P_IRQ_VIC0(30)
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#define IRQ_DISPCON2 S5P_IRQ_VIC0(31)
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/* VIC1 */
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#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
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#define IRQ_PCM0 S5P_IRQ_VIC1(2)
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#define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */
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#define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */
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#define IRQ_UART0 S5P_IRQ_VIC1(5)
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#define IRQ_UART1 S5P_IRQ_VIC1(6)
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#define IRQ_UART2 S5P_IRQ_VIC1(7)
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#define IRQ_UART3 S5P_IRQ_VIC1(8)
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#define IRQ_DMA0 S5P_IRQ_VIC1(9)
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#define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */
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#define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */
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#define IRQ_NFC S5P_IRQ_VIC1(13)
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#define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */
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#define IRQ_SPI0 S5P_IRQ_VIC1(16)
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#define IRQ_SPI1 S5P_IRQ_VIC1(17)
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#define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */
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#define IRQ_IIC S5P_IRQ_VIC1(18)
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#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
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#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
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#define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */
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#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
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#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
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#define IRQ_OTG S5P_IRQ_VIC1(26)
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#define IRQ_DSI S5P_IRQ_VIC1(27)
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#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
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#define IRQ_TSI S5P_IRQ_VIC1(29)
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#define IRQ_PENDN S5P_IRQ_VIC1(30)
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#define IRQ_TC IRQ_PENDN
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#define IRQ_ADC S5P_IRQ_VIC1(31)
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/* UART interrupts, S5P6450 has 5 UARTs */
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#define IRQ_S5P_UART_BASE4 (96)
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#define IRQ_S5P_UART_BASE5 (100)
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#define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
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#define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
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#define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
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#define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
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#define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
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#define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
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/* S3C compatibilty defines */
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#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
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#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
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#define IRQ_I2S0 IRQ_I2SV40
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#define IRQ_LCD_FIFO IRQ_DISPCON0
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#define IRQ_LCD_VSYNC IRQ_DISPCON1
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#define IRQ_LCD_SYSTEM IRQ_DISPCON2
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/* S5P6450 EINT feature will be added */
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/*
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* Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
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* them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
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* after the pair of VICs.
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*/
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#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6)
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#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
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#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE)
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/*
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* S5P6440 has 0-15 external interrupts in group 0. Only these can be used
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* to wake up from sleep. If request is beyond this range, by mistake, a large
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* return value for an irq number should be indication of something amiss.
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*/
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#define S5P_EINT_BASE2 (0xf0000000)
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/*
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* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
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* that they are sourced from the GPIO pins but with a different scheme for
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* priority and source indication.
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*
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* The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
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* interrupts, but for historical reasons they are kept apart from these
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* next interrupts.
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*
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* Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
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* machine specific support files.
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*/
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/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
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#define IRQ_EINT_GROUP1_NR (15)
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#define IRQ_EINT_GROUP2_NR (8)
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#define IRQ_EINT_GROUP5_NR (7)
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#define IRQ_EINT_GROUP6_NR (10)
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/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
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#define IRQ_EINT_GROUP8_NR (11)
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#define IRQ_EINT_GROUP_BASE S5P_EINT(16)
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#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0)
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#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
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#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
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#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
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#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
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#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
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#define IRQ_TIMER_BASE (11)
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/* Set the default NR_IRQS */
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#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
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#endif /* __ASM_ARCH_IRQS_H */
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