447bd47910
P4080 ESDHC controller does not support 1.8V and 3.0V voltage. but the host controller capabilities register wrongly set the bits. This patch adds the workaround to correct the weird voltage setting bits. Only 3.3V voltage is supported for P4080 ESDHC controller. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Cc: Jerry Huang <Chang-Ming.Huang@freescale.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Kumar Gala <galak@gate.crashing.org> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: <linux-mmc@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
556 lines
12 KiB
Text
556 lines
12 KiB
Text
/*
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* P4080DS Device Tree Source
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*
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* Copyright 2009 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "fsl,P4080DS";
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compatible = "fsl,P4080DS";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ccsr = &soc;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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usb0 = &usb0;
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usb1 = &usb1;
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dma0 = &dma0;
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dma1 = &dma1;
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sdhc = &sdhc;
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rio0 = &rapidio0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,4080@0 {
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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};
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};
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cpu1: PowerPC,4080@1 {
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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};
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};
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cpu2: PowerPC,4080@2 {
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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};
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};
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cpu3: PowerPC,4080@3 {
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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};
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};
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cpu4: PowerPC,4080@4 {
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device_type = "cpu";
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reg = <4>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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};
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};
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cpu5: PowerPC,4080@5 {
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device_type = "cpu";
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reg = <5>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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};
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};
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cpu6: PowerPC,4080@6 {
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device_type = "cpu";
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reg = <6>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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};
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};
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cpu7: PowerPC,4080@7 {
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device_type = "cpu";
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reg = <7>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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};
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};
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};
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memory {
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device_type = "memory";
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};
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soc: soc@ffe000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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corenet-law@0 {
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compatible = "fsl,corenet-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <32>;
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};
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memory-controller@8000 {
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compatible = "fsl,p4080-memory-controller";
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reg = <0x8000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <0x12 2>;
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};
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memory-controller@9000 {
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compatible = "fsl,p4080-memory-controller";
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reg = <0x9000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <0x12 2>;
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};
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corenet-cf@18000 {
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compatible = "fsl,corenet-cf";
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reg = <0x18000 0x1000>;
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fsl,ccf-num-csdids = <32>;
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fsl,ccf-num-snoopids = <32>;
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};
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iommu@20000 {
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compatible = "fsl,p4080-pamu";
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reg = <0x20000 0x10000>;
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interrupts = <24 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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dma0: dma@100300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
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reg = <0x100300 0x4>;
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ranges = <0x0 0x100100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <28 2>;
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};
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dma-channel@80 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <29 2>;
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};
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dma-channel@100 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <30 2>;
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};
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dma-channel@180 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <31 2>;
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};
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};
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dma1: dma@101300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
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reg = <0x101300 0x4>;
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ranges = <0x0 0x101100 0x200>;
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cell-index = <1>;
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dma-channel@0 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <32 2>;
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};
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dma-channel@80 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <33 2>;
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};
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dma-channel@100 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <34 2>;
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};
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dma-channel@180 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <35 2>;
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};
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};
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spi@110000 {
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cell-index = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,espi";
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reg = <0x110000 0x1000>;
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interrupts = <53 0x2>;
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interrupt-parent = <&mpic>;
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espi,num-ss-bits = <4>;
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mode = "cpu";
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fsl_m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,espi-flash";
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reg = <0>;
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linux,modalias = "fsl_m25p80";
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spi-max-frequency = <40000000>; /* input clock */
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partition@u-boot {
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label = "u-boot";
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reg = <0x00000000 0x00100000>;
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read-only;
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};
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partition@kernel {
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label = "kernel";
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reg = <0x00100000 0x00500000>;
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read-only;
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};
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partition@dtb {
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label = "dtb";
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reg = <0x00600000 0x00100000>;
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read-only;
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};
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partition@fs {
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label = "file system";
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reg = <0x00700000 0x00900000>;
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};
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};
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};
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sdhc: sdhc@114000 {
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compatible = "fsl,p4080-esdhc", "fsl,esdhc";
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reg = <0x114000 0x1000>;
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interrupts = <48 2>;
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interrupt-parent = <&mpic>;
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voltage-ranges = <3300 3300>;
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sdhci,auto-cmd12;
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};
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i2c@118000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x118000 0x100>;
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interrupts = <38 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@118100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x118100 0x100>;
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interrupts = <38 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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eeprom@51 {
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compatible = "at24,24c256";
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reg = <0x51>;
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};
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eeprom@52 {
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compatible = "at24,24c256";
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reg = <0x52>;
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};
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <0 0x1>;
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interrupt-parent = <&mpic>;
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};
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};
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i2c@119000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <2>;
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compatible = "fsl-i2c";
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reg = <0x119000 0x100>;
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interrupts = <39 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@119100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <3>;
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compatible = "fsl-i2c";
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reg = <0x119100 0x100>;
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interrupts = <39 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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serial0: serial@11c500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11c500 0x100>;
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clock-frequency = <0>;
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interrupts = <36 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@11c600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11c600 0x100>;
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clock-frequency = <0>;
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interrupts = <36 2>;
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interrupt-parent = <&mpic>;
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};
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serial2: serial@11d500 {
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cell-index = <2>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11d500 0x100>;
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clock-frequency = <0>;
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interrupts = <37 2>;
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interrupt-parent = <&mpic>;
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};
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serial3: serial@11d600 {
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cell-index = <3>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11d600 0x100>;
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clock-frequency = <0>;
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interrupts = <37 2>;
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interrupt-parent = <&mpic>;
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};
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gpio0: gpio@130000 {
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compatible = "fsl,p4080-gpio";
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reg = <0x130000 0x1000>;
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interrupts = <55 2>;
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interrupt-parent = <&mpic>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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usb0: usb@210000 {
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compatible = "fsl,p4080-usb2-mph",
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"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
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reg = <0x210000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <44 0x2>;
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phy_type = "ulpi";
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};
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usb1: usb@211000 {
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compatible = "fsl,p4080-usb2-dr",
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"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
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reg = <0x211000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <45 0x2>;
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dr_mode = "host";
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phy_type = "ulpi";
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};
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};
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rapidio0: rapidio@ffe0c0000 {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "fsl,rapidio-delta";
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reg = <0xf 0xfe0c0000 0 0x20000>;
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ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
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interrupt-parent = <&mpic>;
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/* err_irq bell_outb_irq bell_inb_irq
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msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
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interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
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};
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localbus@ffe124000 {
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compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
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reg = <0xf 0xfe124000 0 0x1000>;
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interrupts = <25 2>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0xf 0xe8000000 0x08000000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x08000000>;
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bank-width = <2>;
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device-width = <2>;
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};
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};
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pci0: pcie@ffe200000 {
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compatible = "fsl,p4080-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xf 0xfe200000 0 0x1000>;
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bus-range = <0x0 0xff>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
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0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
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clock-frequency = <0x1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 40 1
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0000 0 0 2 &mpic 1 1
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0000 0 0 3 &mpic 2 1
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0000 0 0 4 &mpic 3 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci1: pcie@ffe201000 {
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compatible = "fsl,p4080-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xf 0xfe201000 0 0x1000>;
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bus-range = <0 0xff>;
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ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
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clock-frequency = <0x1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 41 1
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0000 0 0 2 &mpic 5 1
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0000 0 0 3 &mpic 6 1
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0000 0 0 4 &mpic 7 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci2: pcie@ffe202000 {
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compatible = "fsl,p4080-pcie";
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|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xf 0xfe202000 0 0x1000>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
|
|
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
|
clock-frequency = <0x1fca055>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <16 2>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0 0 1 &mpic 42 1
|
|
0000 0 0 2 &mpic 9 1
|
|
0000 0 0 3 &mpic 10 1
|
|
0000 0 0 4 &mpic 11 1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0 0 0 0 0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x02000000 0 0xe0000000
|
|
0x02000000 0 0xe0000000
|
|
0 0x20000000
|
|
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0x00000000
|
|
0 0x00010000>;
|
|
};
|
|
};
|
|
|
|
};
|