0d152c27e3
SMP systems require per-cpu local clock event devices in order to enable HRT support. One a BF561, we can use local core timer for this purpose. Originally, there was one global core-timer clock event device set up for core A. To accomplish this feat, we need to split the gptimer0/core timer logic so that each is a standalone clock event. There is no requirement that we only have one clock event source anyways. Once we have this, we just define per-cpu clock event devices for each local core timer. Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/*
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* asm-blackfin/time.h:
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*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _ASM_BLACKFIN_TIME_H
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#define _ASM_BLACKFIN_TIME_H
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/*
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* The way that the Blackfin core timer works is:
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* - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
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* - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
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*
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* If you take the fastest clock (1ns, or 1GHz to make the math work easier)
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* 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
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* (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
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* to use TSCALE, and program it to zero (which is pass CCLK through).
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* If you feel like using it, try to keep HZ * TIMESCALE to some
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* value that divides easy (like power of 2).
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*/
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#ifndef CONFIG_CPU_FREQ
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#define TIME_SCALE 1
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#define __bfin_cycles_off (0)
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#define __bfin_cycles_mod (0)
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#else
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/*
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* Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
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* Whenever we change the Core Clock frequency changes we immediately
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* adjust the Core Timer Presale Register. This way we don't lose time.
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*/
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#define TIME_SCALE 4
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extern unsigned long long __bfin_cycles_off;
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extern unsigned int __bfin_cycles_mod;
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#endif
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#if defined(CONFIG_TICKSOURCE_CORETMR)
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extern void bfin_coretmr_init(void);
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extern void bfin_coretmr_clockevent_init(void);
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#endif
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#endif
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