c41136b05d
This patch disable the optional PM feature inside the Hudson3 platform under the following conditions: 1. If an isochronous device is connected to xHCI port and is active; 2. Optional PM feature that powers down the internal Bus PLL when the link is in low power state is enabled. The PM feature needs to be disabled to eliminate PLL startup delays when the link comes out of low power state. The performance of DMA data transfer could be impacted if system delay were encountered and in addition to the PLL start up delays. Disabling the PM would leave room for unpredictable system delays in order to guarantee uninterrupted data transfer to isochronous audio or video stream devices that require time sensitive information. If data in an audio/video stream was interrupted then erratic audio or video performance may be encountered. AMD PLL quirk is already implemented in OHCI/EHCI driver. After moving the quirk code to pci-quirks.c and export them, xHCI driver can call it directly without having the quirk implementation in itself. Signed-off-by: Andiry Xu <andiry.xu@amd.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
341 lines
9.2 KiB
C
341 lines
9.2 KiB
C
/*
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* xHCI host controller driver PCI Bus Glue.
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/pci.h>
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#include "xhci.h"
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/* Device for a quirk */
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#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
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#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
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static const char hcd_name[] = "xhci_hcd";
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/* called after powerup, by probe or system-pm "wakeup" */
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static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
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{
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/*
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* TODO: Implement finding debug ports later.
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* TODO: see if there are any quirks that need to be added to handle
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* new extended capabilities.
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*/
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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if (!pci_set_mwi(pdev))
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xhci_dbg(xhci, "MWI active\n");
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xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
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return 0;
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}
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/* called during probe() after chip reset completes */
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static int xhci_pci_setup(struct usb_hcd *hcd)
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{
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struct xhci_hcd *xhci;
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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int retval;
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u32 temp;
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hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
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if (usb_hcd_is_primary_hcd(hcd)) {
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xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
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if (!xhci)
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return -ENOMEM;
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*((struct xhci_hcd **) hcd->hcd_priv) = xhci;
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xhci->main_hcd = hcd;
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/* Mark the first roothub as being USB 2.0.
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* The xHCI driver will register the USB 3.0 roothub.
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*/
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hcd->speed = HCD_USB2;
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hcd->self.root_hub->speed = USB_SPEED_HIGH;
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/*
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* USB 2.0 roothub under xHCI has an integrated TT,
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* (rate matching hub) as opposed to having an OHCI/UHCI
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* companion controller.
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*/
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hcd->has_tt = 1;
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} else {
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/* xHCI private pointer was set in xhci_pci_probe for the second
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* registered roothub.
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*/
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xhci = hcd_to_xhci(hcd);
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temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
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if (HCC_64BIT_ADDR(temp)) {
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xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
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dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
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} else {
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dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
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}
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return 0;
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}
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xhci->cap_regs = hcd->regs;
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xhci->op_regs = hcd->regs +
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HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
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xhci->run_regs = hcd->regs +
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(xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
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/* Cache read-only capability registers */
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xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
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xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
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xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
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xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
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xhci->hci_version = HC_VERSION(xhci->hcc_params);
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xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
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xhci_print_registers(xhci);
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/* Look for vendor-specific quirks */
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if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
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pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
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pdev->revision == 0x0) {
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xhci->quirks |= XHCI_RESET_EP_QUIRK;
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xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
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" endpoint cmd after reset endpoint\n");
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}
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if (pdev->vendor == PCI_VENDOR_ID_NEC)
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xhci->quirks |= XHCI_NEC_HOST;
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/* AMD PLL quirk */
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if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
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xhci->quirks |= XHCI_AMD_PLL_FIX;
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/* Make sure the HC is halted. */
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retval = xhci_halt(xhci);
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if (retval)
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goto error;
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xhci_dbg(xhci, "Resetting HCD\n");
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/* Reset the internal HC memory state and registers. */
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retval = xhci_reset(xhci);
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if (retval)
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goto error;
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xhci_dbg(xhci, "Reset complete\n");
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temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
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if (HCC_64BIT_ADDR(temp)) {
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xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
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dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
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} else {
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dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
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}
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xhci_dbg(xhci, "Calling HCD init\n");
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/* Initialize HCD and host controller data structures. */
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retval = xhci_init(hcd);
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if (retval)
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goto error;
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xhci_dbg(xhci, "Called HCD init\n");
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pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
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xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
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/* Find any debug ports */
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retval = xhci_pci_reinit(xhci, pdev);
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if (!retval)
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return retval;
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error:
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kfree(xhci);
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return retval;
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}
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/*
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* We need to register our own PCI probe function (instead of the USB core's
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* function) in order to create a second roothub under xHCI.
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*/
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static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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int retval;
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struct xhci_hcd *xhci;
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struct hc_driver *driver;
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struct usb_hcd *hcd;
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driver = (struct hc_driver *)id->driver_data;
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/* Register the USB 2.0 roothub.
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* FIXME: USB core must know to register the USB 2.0 roothub first.
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* This is sort of silly, because we could just set the HCD driver flags
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* to say USB 2.0, but I'm not sure what the implications would be in
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* the other parts of the HCD code.
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*/
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retval = usb_hcd_pci_probe(dev, id);
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if (retval)
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return retval;
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/* USB 2.0 roothub is stored in the PCI device now. */
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hcd = dev_get_drvdata(&dev->dev);
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xhci = hcd_to_xhci(hcd);
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xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
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pci_name(dev), hcd);
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if (!xhci->shared_hcd) {
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retval = -ENOMEM;
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goto dealloc_usb2_hcd;
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}
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/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
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* is called by usb_add_hcd().
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*/
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*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
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retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
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IRQF_DISABLED | IRQF_SHARED);
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if (retval)
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goto put_usb3_hcd;
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/* Roothub already marked as USB 3.0 speed */
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return 0;
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put_usb3_hcd:
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usb_put_hcd(xhci->shared_hcd);
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dealloc_usb2_hcd:
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usb_hcd_pci_remove(dev);
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return retval;
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}
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static void xhci_pci_remove(struct pci_dev *dev)
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{
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struct xhci_hcd *xhci;
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xhci = hcd_to_xhci(pci_get_drvdata(dev));
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if (xhci->shared_hcd) {
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usb_remove_hcd(xhci->shared_hcd);
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usb_put_hcd(xhci->shared_hcd);
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}
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usb_hcd_pci_remove(dev);
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kfree(xhci);
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}
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#ifdef CONFIG_PM
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static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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int retval = 0;
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if (hcd->state != HC_STATE_SUSPENDED ||
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xhci->shared_hcd->state != HC_STATE_SUSPENDED)
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return -EINVAL;
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retval = xhci_suspend(xhci);
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return retval;
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}
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static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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int retval = 0;
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retval = xhci_resume(xhci, hibernated);
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return retval;
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}
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#endif /* CONFIG_PM */
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static const struct hc_driver xhci_pci_hc_driver = {
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.description = hcd_name,
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.product_desc = "xHCI Host Controller",
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.hcd_priv_size = sizeof(struct xhci_hcd *),
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/*
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* generic hardware linkage
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*/
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.irq = xhci_irq,
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.flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
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/*
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* basic lifecycle operations
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*/
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.reset = xhci_pci_setup,
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.start = xhci_run,
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#ifdef CONFIG_PM
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.pci_suspend = xhci_pci_suspend,
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.pci_resume = xhci_pci_resume,
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#endif
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.stop = xhci_stop,
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.shutdown = xhci_shutdown,
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/*
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* managing i/o requests and associated device resources
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*/
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.urb_enqueue = xhci_urb_enqueue,
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.urb_dequeue = xhci_urb_dequeue,
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.alloc_dev = xhci_alloc_dev,
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.free_dev = xhci_free_dev,
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.alloc_streams = xhci_alloc_streams,
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.free_streams = xhci_free_streams,
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.add_endpoint = xhci_add_endpoint,
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.drop_endpoint = xhci_drop_endpoint,
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.endpoint_reset = xhci_endpoint_reset,
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.check_bandwidth = xhci_check_bandwidth,
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.reset_bandwidth = xhci_reset_bandwidth,
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.address_device = xhci_address_device,
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.update_hub_device = xhci_update_hub_device,
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.reset_device = xhci_discover_or_reset_device,
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/*
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* scheduling support
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*/
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.get_frame_number = xhci_get_frame,
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/* Root hub support */
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.hub_control = xhci_hub_control,
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.hub_status_data = xhci_hub_status_data,
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.bus_suspend = xhci_bus_suspend,
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.bus_resume = xhci_bus_resume,
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};
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/*-------------------------------------------------------------------------*/
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/* PCI driver selection metadata; PCI hotplugging uses this */
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static const struct pci_device_id pci_ids[] = { {
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/* handle any USB 3.0 xHCI controller */
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PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
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.driver_data = (unsigned long) &xhci_pci_hc_driver,
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},
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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/* pci driver glue; this is a "new style" PCI driver module */
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static struct pci_driver xhci_pci_driver = {
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.name = (char *) hcd_name,
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.id_table = pci_ids,
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.probe = xhci_pci_probe,
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.remove = xhci_pci_remove,
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/* suspend and resume implemented later */
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.shutdown = usb_hcd_pci_shutdown,
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#ifdef CONFIG_PM_SLEEP
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.driver = {
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.pm = &usb_hcd_pci_pm_ops
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},
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#endif
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};
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int xhci_register_pci(void)
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{
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return pci_register_driver(&xhci_pci_driver);
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}
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void xhci_unregister_pci(void)
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{
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pci_unregister_driver(&xhci_pci_driver);
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}
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