57015421d3
The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
145 lines
5.4 KiB
C
145 lines
5.4 KiB
C
/****************************************************************************/
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/*
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* m523xsim.h -- ColdFire 523x System Integration Module support.
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*
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* (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
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*/
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/****************************************************************************/
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#ifndef m523xsim_h
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#define m523xsim_h
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/****************************************************************************/
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#define CPU_NAME "COLDFIRE(m523x)"
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#define CPU_INSTR_PER_JIFFY 3
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/*
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* Define the 523x SIM register set addresses.
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*/
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#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
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#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_IRLR 0x18 /* */
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#define MCFINTC_IACKL 0x19 /* */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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#define MCFINT_VECBASE 64 /* Vector base number */
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#define MCFINT_UART0 13 /* Interrupt number for UART0 */
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#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
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#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
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/*
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* SDRAM configuration registers.
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*/
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#define MCFSIM_DCR 0x44 /* SDRAM control */
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#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
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#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
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#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
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#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
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/*
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* Reset Controll Unit (relative to IPSBAR).
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*/
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#define MCF_RCR 0x110000
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#define MCF_RSR 0x110001
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#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
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#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
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/*
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* UART module.
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*/
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#define MCFUART_BASE1 0x200 /* Base address of UART1 */
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#define MCFUART_BASE2 0x240 /* Base address of UART2 */
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#define MCFUART_BASE3 0x280 /* Base address of UART3 */
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#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
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#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
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#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
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#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
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#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
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#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
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#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
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#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
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#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
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#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
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#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
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#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
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#define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
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#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
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#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
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#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
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#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
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#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
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#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
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#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
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#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
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#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
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#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
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#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
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#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
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#define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
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#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
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#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
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#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
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#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
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#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
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#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
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#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
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#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
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#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
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#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
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#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
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#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
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#define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
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#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
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#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
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#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
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#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
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#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
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#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
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#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
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#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
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#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
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#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
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#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
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#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
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#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
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/*
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* EPort
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*/
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#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
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#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
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#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
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#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
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#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
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#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
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#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
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#define MCFGPIO_PIN_MAX 107
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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/*
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* Pin Assignment
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*/
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#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
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#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
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/****************************************************************************/
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#endif /* m523xsim_h */
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